Apply generic to IP.

libraries/technology/ip_arria10/ip_arria10_ram_crw_crw.vhd

@@ -39,35 +39,48 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_lnsim;
 USE altera_lnsim.altera_lnsim_components.all;
 
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
 ENTITY ip_arria10_ram_crw_crw IS
+  GENERIC (
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
 	PORT
 	(
-		address_a		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
-		address_b		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+		address_a		: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
 		clock_a		: IN STD_LOGIC  := '1';
 		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		data_a		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 		enable_a		: IN STD_LOGIC  := '1';
 		enable_b		: IN STD_LOGIC  := '1';
 		rden_a		: IN STD_LOGIC  := '1';
 		rden_b		: IN STD_LOGIC  := '1';
 		wren_a		: IN STD_LOGIC  := '0';
 		wren_b		: IN STD_LOGIC  := '0';
-		q_a		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
-		q_b		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+		q_a		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
 	);
 END ip_arria10_ram_crw_crw;
 
 
 ARCHITECTURE SYN OF ip_arria10_ram_crw_crw IS
 
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (17 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (17 DOWNTO 0);
+  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+  
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
 
 BEGIN
-	q_a    <= sub_wire0(17 DOWNTO 0);
-	q_b    <= sub_wire1(17 DOWNTO 0);
+	q_a    <= sub_wire0(g_dat_w-1 DOWNTO 0);
+	q_b    <= sub_wire1(g_dat_w-1 DOWNTO 0);
 
 	altera_syncram_component : altera_syncram
 	GENERIC MAP (
@@ -77,23 +90,23 @@ BEGIN
 		clock_enable_output_a => "BYPASS",
 		clock_enable_output_b => "BYPASS",
 		indata_reg_b => "CLOCK1",
-		init_file => "fft_3n1024sin.hex",
+		init_file => g_init_file,
 		intended_device_family => "Arria 10",
 		lpm_type => "altera_syncram",
-		numwords_a => 32,
-		numwords_b => 32,
+		numwords_a => g_nof_words,
+		numwords_b => g_nof_words,
 		operation_mode => "BIDIR_DUAL_PORT",
 		outdata_aclr_a => "NONE",
 		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
+		outdata_reg_a => c_outdata_reg_a,
+		outdata_reg_b => c_outdata_reg_b,
 		power_up_uninitialized => "FALSE",
 		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
 		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => 5,
-		widthad_b => 5,
-		width_a => 18,
-		width_b => 18,
+		widthad_a => g_adr_w,
+		widthad_b => g_adr_w,
+		width_a => g_dat_w,
+		width_b => g_dat_w,
 		width_byteena_a => 1,
 		width_byteena_b => 1
 	)