L2SDP-180, add mms_* bus and tb_mms_*

libraries/base/common/hdllib.cfg

@@ -130,6 +130,7 @@ synth_files =
     src/vhdl/common_shiftram.vhd
 
     src/vhdl/common_variable_delay.vhd
+    src/vhdl/mms_common_variable_delay.vhd
     
     src/vhdl/mms_common_reg.vhd
     src/vhdl/mms_common_stable_monitor.vhd
@@ -189,6 +190,7 @@ test_bench_files =
     tb/vhdl/tb_common_transpose_symbol.vhd
     tb/vhdl/tb_common_zip.vhd
     tb/vhdl/tb_common_variable_delay.vhd
+    tb/vhdl/tb_mms_common_variable_delay.vhd
     tb/vhdl/tb_requantize.vhd
     tb/vhdl/tb_resize.vhd
     tb/vhdl/tb_round.vhd

libraries/base/common/src/vhdl/mms_common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . mm interface for common_variable_delay.vhd to enable output
+-- Description:
+-- . see common_variable_delay.vhd
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+
+ENTITY mms_common_variable_delay IS
+  PORT (
+    mm_rst          : IN  STD_LOGIC;
+    mm_clk          : IN  STD_LOGIC;
+    dp_rst          : IN  STD_LOGIC := '0';
+    dp_clk          : IN  STD_LOGIC;
+
+    -- MM interface
+    reg_enable_mosi : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_enable_miso : OUT t_mem_miso;
+
+    delay           : IN  NATURAL := 0;
+    trigger         : IN  STD_LOGIC := '0';
+    trigger_dly     : OUT STD_LOGIC
+  );
+END mms_common_variable_delay;
+
+
+ARCHITECTURE rtl OF mms_common_variable_delay IS
+  
+  CONSTANT c_enable_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
+  
+  SIGNAL enable_reg : STD_LOGIC_VECTOR(c_enable_mem_reg.dat_w*c_enable_mem_reg.nof_dat-1 DOWNTO 0);
+
+  SIGNAL enable : STD_LOGIC := '0';
+
+
+BEGIN
+  enable <= sl(enable_reg);
+  
+  -- device under test
+  u_dut : ENTITY work.common_variable_delay
+  PORT MAP (
+    rst     => dp_rst,
+    clk     => dp_clk,
+
+    delay   => delay,
+    enable  => enable,
+    in_val  => trigger,
+    out_val => trigger_dly
+  );
+
+  u_mms_common_reg : ENTITY work.mms_common_reg
+  GENERIC MAP (
+    g_mm_reg       => c_enable_mem_reg
+  )
+  PORT MAP (
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+
+    reg_mosi       => reg_enable_mosi,
+    reg_miso       => reg_enable_miso,
+
+    in_reg         => enable_reg,
+    out_reg        => enable_reg   
+  );
+
+END;
\ No newline at end of file

libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd

@@ -22,7 +22,7 @@
 -- Purpose:
 -- . test bench for common_variable_delay.vhd
 -- Description:
--- . see common_variable_delay.vhd
+-- . see common_variable_delay
 -- --------------------------------------------------------------------------
 
 

libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd

+-- --------------------------------------------------------------------------
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+
+-- --------------------------------------------------------------------------
+-- Author:
+-- . Pieter Donker
+-- Purpose:
+-- . test bench for common_variable_delay.vhd to test enable by signal mm interface
+-- Description:
+-- . see common_variable_delay.vhd
+-- --------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE work.common_pkg.ALL;
+USE work.common_str_pkg.ALL;
+USE work.tb_common_pkg.ALL;
+USE work.common_mem_pkg.ALL;
+USE work.tb_common_mem_pkg.ALL; 
+
+ENTITY tb_mms_common_variable_delay IS
+END tb_mms_common_variable_delay;
+
+ARCHITECTURE tb OF tb_mms_common_variable_delay IS
+  CONSTANT c_clk_period       : TIME    := 10 ns;
+  CONSTANT c_trigger_interval : NATURAL := 40;  -- in clk's
+  CONSTANT c_mm_addr_enable   : NATURAL := 0;
+  CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
+  
+  SIGNAL tb_end : STD_LOGIC := '0';
+  SIGNAL rst    : STD_LOGIC;
+  SIGNAL clk    : STD_LOGIC := '0';
+  
+  SIGNAL delay       : NATURAL   := 0;
+  SIGNAL trigger     : STD_LOGIC := '0';
+  SIGNAL trigger_dly : STD_LOGIC := '0';
+
+  SIGNAL mm_mosi     : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL mm_miso     : t_mem_miso;
+
+  SIGNAL enable      : NATURAL;
+BEGIN
+  clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+  rst <= '1', '0' AFTER c_clk_period*4;
+
+  p_mm_stimuli : PROCESS
+  BEGIN
+    WAIT UNTIL rst='0';
+    proc_common_wait_some_cycles(clk, 10);
+
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 0, clk, mm_miso, mm_mosi);
+    proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+    proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_rd_latency(1, clk);
+    enable <= TO_UINT(mm_miso.rddata(0 DOWNTO 0));
+    ASSERT enable = 0 REPORT "enable not off" SEVERITY ERROR;
+     
+    proc_mem_mm_bus_wr(c_mm_addr_enable, 1, clk, mm_miso, mm_mosi);
+    proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
+    proc_mem_mm_bus_rd(c_mm_addr_enable, clk, mm_miso, mm_mosi);
+    proc_mem_mm_bus_rd_latency(1, clk);
+    enable <= TO_UINT(mm_miso.rddata(1 DOWNTO 0));
+    ASSERT enable = 1 REPORT "enable not on" SEVERITY ERROR;
+
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+
+  -- generate trigger signal
+  p_trigger : PROCESS
+  BEGIN
+    WAIT UNTIL rst = '0';
+    proc_common_wait_some_cycles(clk, 10);
+    WAIT UNTIL rising_edge(clk);
+    WHILE tb_end = '0' LOOP
+      trigger <= NOT trigger;
+      proc_common_wait_some_cycles(clk, c_trigger_interval/2);
+    END LOOP;
+    WAIT;
+  END PROCESS;
+
+  -- device under test
+  u_dut : ENTITY work.mms_common_variable_delay
+  PORT MAP (
+    mm_rst     => rst,
+    mm_clk     => clk,
+    dp_rst     => rst,
+    dp_clk     => clk,
+
+    reg_enable_mosi => mm_mosi,
+    reg_enable_miso => mm_miso,
+
+    delay       => delay,
+    trigger     => trigger,
+    trigger_dly => trigger_dly
+  );
+      
+END tb;
+