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Commit 3b91b974 authored by Pieter Donker's avatar Pieter Donker
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fixed bug in u_common_pipeline_sl, g_pipeline has now the right value

parent 564432fe
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libraries/base/dp/src/vhdl/dp_complex_add.vhd
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...@@ -109,7 +109,7 @@ BEGIN ...@@ -109,7 +109,7 @@ BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
GENERIC MAP ( GENERIC MAP (
g_pipeline => c_pipeline g_pipeline => c_pipeline*ceil_log2(g_nof_inputs)
) )
PORT MAP ( PORT MAP (
rst => rst, rst => rst,
......
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