Removed unused pi_ddr3. Added ddr.write_flush_pulse().

boards/uniboard1/designs/unb1_ddr3/tb/python/tc_unb1_ddr3_seq.py

@@ -33,7 +33,6 @@ Usage:
 # System imports
 import test_case
 import node_io
-import pi_ddr3
 import pi_diag_block_gen
 import pi_diag_tx_seq
 import pi_diag_data_buffer
@@ -61,17 +60,12 @@ io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
     
 # Create instances for the periperals
 c_nof_streams = 1
-c_nof_ddr3    = 1 # possible options: 1 or 2
 
 bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, nofChannels=c_nof_streams, ramSizePerChannel=2**14)
 db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, nofStreams=c_nof_streams)
 tx_seq = pi_diag_tx_seq.PiDiagTxSeq(tc, io, nof_inst=c_nof_streams)
 rx_seq = pi_diag_rx_seq.PiDiagRxSeq(tc, io, nof_inst=c_nof_streams)
 
-ddr3 = []
-for i in range(c_nof_ddr3):
-  ddr3.append(pi_ddr3.PiDDR3(tc, io, [i]))
-
 # Create object for DDR register map
 ddr = pi_io_ddr.PiIoDdr(tc, io, nof_inst = 1)
 
@@ -88,11 +82,15 @@ rx_seq.write_disable()
 # Read RX Sequencer result before run
 rx_seq.read_result()
 
-# Wait for the DDR3 to become available    
+# Wait for the DDR memory to become available    
 #ddr.read_io_ddr()
 do_until_eq(ddr.read_init_done, ms_retry=3000, val=1, s_timeout=3600)        
 
-# Set DDR3 controller in write mode and start writing
+# Flush Tx FIFO
+ddr.write_flush_pulse()
+io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
+
+# Set DDR controller in write mode and start writing
 start_address = 0
 nof_words = 100
 ddr.set_address(data=start_address)