Define tr_xaui_mdio outside tr_xaui, to prepare for using tech_eth_10g instead...

Define tr_xaui_mdio outside tr_xaui, to prepare for using tech_eth_10g instead of tech_mac_10g + tr_xaui.

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -272,19 +272,39 @@ BEGIN
 
     -- XAUI PHY IP MM control/status
     xaui_mosi               => xaui_mosi,
-    xaui_miso               => xaui_miso,
-      
-    -- MDIO master = mm slave
-    mdio_mosi_arr           => mdio_mosi_arr(g_nof_macs-1 DOWNTO 0),
-    mdio_miso_arr           => mdio_miso_arr(g_nof_macs-1 DOWNTO 0),
-
-    -- MDIO External clock and serial data.
-    mdio_rst                => mdio_rst,
-    mdio_mdc                => mdio_mdc_arr,
-    mdio_mdat_in            => mdio_mdat_in_arr,
-    mdio_mdat_oen           => mdio_mdat_oen_arr
+    xaui_miso               => xaui_miso      
   );
 
+  ---------------------------------------------------------------------------
+  -- MDIO
+  ---------------------------------------------------------------------------
+  gen_mdio: IF g_use_mdio = TRUE GENERATE
+    u_tr_xaui_mdio : ENTITY tr_xaui_lib.tr_xaui_mdio
+    GENERIC MAP (
+      g_sim           => g_sim,
+      g_nof_xaui      => g_nof_macs,
+      g_mdio_epcs_dis => g_mdio_epcs_dis
+    )
+    PORT MAP (
+      -- Transceiver PLL reference clock   
+      tr_clk            => tr_clk,
+      tr_rst            => tr_rst,
+    
+      -- MM clock for register of optional MDIO master
+      mm_clk            => mm_clk,
+      mm_rst            => mm_rst,
+    
+      -- MDIO master = mm slave
+      mdio_mosi_arr     => mdio_mosi_arr,
+      mdio_miso_arr     => mdio_miso_arr,
+    
+      -- MDIO External clock and serial data.
+      mdio_rst          => mdio_rst,
+      mdio_mdc_arr      => mdio_mdc_arr,
+      mdio_mdat_in_arr  => mdio_mdat_in_arr,
+      mdio_mdat_oen_arr => mdio_mdat_oen_arr
+    );
+  END GENERATE;
 
   ---------------------------------------------------------------------------------------
   -- RX FIFO: rx_clk -> dp_clk