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Commit 39c5502c authored by Eric Kooistra's avatar Eric Kooistra
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Insert eth_tester for 1GbE I and II.

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1 merge request!292Use default 0 for nxt_info to avoid X to decimal conversion error in sim_io.py...
Pipeline #39600 passed
Stage: simulation
Stage: synthesis
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boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+ 180
− 109
View file @ 39c5502c
......@@ -33,6 +33,7 @@ USE unb2c_board_lib.unb2c_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE eth_lib.eth_pkg.ALL;
USE eth_lib.eth_tester_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.unb2c_test_pkg.ALL;
USE util_lib.util_heater_pkg.ALL;
......@@ -131,8 +132,6 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_fw_version : t_unb2c_board_fw_version := (2, 0);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_125M;
-- Revision controlled constants
CONSTANT c_revision_select : t_unb2c_test_config := func_sel_revision_rec(g_design_name);
CONSTANT c_use_loopback : BOOLEAN := c_revision_select.use_loopback;
......@@ -156,10 +155,13 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_nof_jesd204b : NATURAL := c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w;
-- 1GbE
-- This is the number of UDP offload streams. Fix it to 2 when UDP offload is enabled
-- CONSTANT c_nof_streams_1GbE_UDP : NATURAL := sel_a_b(c_use_1GbE_I,1,0) + sel_a_b(c_use_1GbE_II,1,0);
CONSTANT c_nof_streams_1GbE_UDP : NATURAL := sel_a_b(c_use_1GbE_I_UDP,2,0);
CONSTANT c_base_ip_II : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A64"; -- Placeholder base IP address for eth1 10.100.xx.yy
CONSTANT c_nof_udp_streams_1GbE_I : NATURAL := 4; -- <= c_eth_nof_udp_ports = 4, shared with M&C stream
CONSTANT c_nof_udp_streams_1GbE_I_w : NATURAL := 2; -- = true_log2(c_nof_udp_streams_1GbE_I), fixed reserve 2 bit extra MM address space
CONSTANT c_nof_udp_streams_1GbE_II : NATURAL := 1; -- fixed 1 UDP stream, so no need for dp_mux
CONSTANT c_nof_udp_streams_1GbE_II_w : NATURAL := 0; -- = true_log2(c_nof_udp_streams_1GbE_II), fixed reserve no extra MM address space
CONSTANT c_base_mac : STD_LOGIC_VECTOR(32-1 DOWNTO 0) := c_eth_tester_eth_src_mac_47_16; -- = X"00228608"
CONSTANT c_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := c_eth_tester_ip_src_addr_31_16; -- = X"0A63"
CONSTANT c_base_udp : STD_LOGIC_VECTOR(8-1 DOWNTO 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
-- 10GbE
CONSTANT c_nof_streams_qsfp : NATURAL := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
......@@ -192,22 +194,20 @@ ARCHITECTURE str OF unb2c_test IS
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_use_jumbo_frames : BOOLEAN := FALSE;
CONSTANT c_def_1GbE_block_size : NATURAL := 20; -- 0 first so we have time to set RX demux reg in dest. node
CONSTANT c_def_10GbE_block_size : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
CONSTANT c_max_frame_len : NATURAL := sel_a_b(c_use_jumbo_frames, 9018, 1518);
CONSTANT c_nof_header_bytes : NATURAL := field_slv_len(c_hdr_field_arr) / c_byte_w;
CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_nof_header_bytes-c_network_eth_crc_len;
CONSTANT c_max_udp_payload_nof_words_1GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_32;
CONSTANT c_max_udp_payload_nof_words_10GbE : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w_64;
CONSTANT c_min_nof_words_per_block : NATURAL := 1;
CONSTANT c_max_nof_blocks_per_packet_1GbE : NATURAL := c_max_udp_payload_nof_words_1GbE/c_min_nof_words_per_block;
CONSTANT c_max_nof_blocks_per_packet_10GbE : NATURAL := c_max_udp_payload_nof_words_10GbE/c_min_nof_words_per_block;
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL gn_index : NATURAL;
SIGNAL ext_clk200 : STD_LOGIC;
SIGNAL ext_rst200 : STD_LOGIC;
......@@ -221,6 +221,7 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mb_I_ref_rst : STD_LOGIC;
SIGNAL mb_II_ref_rst : STD_LOGIC;
......@@ -319,7 +320,6 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso;
-- Heater
SIGNAL reg_heater_mosi : t_mem_mosi;
SIGNAL reg_heater_miso : t_mem_miso;
......@@ -360,6 +360,23 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_eth10g_back0_mosi : t_mem_mosi;
SIGNAL reg_eth10g_back0_miso : t_mem_miso;
-- 1GbE I eth_tester (c_nof_udp_streams_1GbE_I_w = 2 bit)
-- . Tx
SIGNAL reg_eth1g_I_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 5
SIGNAL reg_eth1g_I_bg_ctrl_cipo : t_mem_cipo;
SIGNAL reg_eth1g_I_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 7
SIGNAL reg_eth1g_I_hdr_dat_cipo : t_mem_cipo;
SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
SIGNAL reg_eth1g_I_bsn_monitor_v2_tx_cipo : t_mem_cipo;
SIGNAL reg_eth1g_I_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
SIGNAL reg_eth1g_I_strobe_total_count_tx_cipo : t_mem_cipo;
-- . Rx
SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 5
SIGNAL reg_eth1g_I_bsn_monitor_v2_rx_cipo : t_mem_cipo;
SIGNAL reg_eth1g_I_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 7
SIGNAL reg_eth1g_I_strobe_total_count_rx_cipo : t_mem_cipo;
--REMOVEME
SIGNAL reg_diag_bg_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_1GbE_miso : t_mem_miso;
SIGNAL ram_diag_bg_1GbE_mosi : t_mem_mosi;
......@@ -367,6 +384,33 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_tx_seq_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_tx_seq_1GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi; --
SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso; --
SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi; --
SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso; --
SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
--REMOVEME
-- 1GbE II eth_tester (c_nof_udp_streams_1GbE_I_w = 0 bit)
-- . Tx
SIGNAL reg_eth1g_II_bg_ctrl_copi : t_mem_copi := c_mem_copi_rst; -- c_diag_bg_reg_adr_w = 3 --> w = 3
SIGNAL reg_eth1g_II_bg_ctrl_cipo : t_mem_cipo;
SIGNAL reg_eth1g_II_hdr_dat_copi : t_mem_copi := c_mem_copi_rst; -- c_eth_tester_reg_hdr_dat_addr_w = 5 --> w = 5
SIGNAL reg_eth1g_II_hdr_dat_cipo : t_mem_cipo;
SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
SIGNAL reg_eth1g_II_bsn_monitor_v2_tx_cipo : t_mem_cipo;
SIGNAL reg_eth1g_II_strobe_total_count_tx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
SIGNAL reg_eth1g_II_strobe_total_count_tx_cipo : t_mem_cipo;
-- . Rx
SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_bsn_monitor_v2_reg_adr_w = 3 --> w = 3
SIGNAL reg_eth1g_II_bsn_monitor_v2_rx_cipo : t_mem_cipo;
SIGNAL reg_eth1g_II_strobe_total_count_rx_copi : t_mem_copi := c_mem_copi_rst; -- c_dp_strobe_total_count_reg_adr_w = 5 --> w = 5
SIGNAL reg_eth1g_II_strobe_total_count_rx_cipo : t_mem_cipo;
-- 10GbE
SIGNAL reg_diag_bg_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_10GbE_miso : t_mem_miso;
SIGNAL ram_diag_bg_10GbE_mosi : t_mem_mosi;
......@@ -374,18 +418,9 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_tx_seq_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_tx_seq_10GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_1GbE_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_1GbE_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_10GbE_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_10GbE_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_1GbE_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_1GbE_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_1GbE_miso : t_mem_miso;
SIGNAL reg_diag_rx_seq_1GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_1GbE_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_10GbE_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_10GbE_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_10GbE_mosi : t_mem_mosi;
......@@ -393,11 +428,6 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL reg_diag_rx_seq_10GbE_mosi : t_mem_mosi;
SIGNAL reg_diag_rx_seq_10GbE_miso : t_mem_miso;
SIGNAL dp_offload_tx_1GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL dp_offload_tx_1GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL dp_offload_rx_1GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL dp_offload_rx_1GbE_snk_out_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL dp_offload_tx_10GbE_src_out_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_tx_10GbE_src_in_arr : t_dp_siso_arr(c_nof_streams_10GbE-1 DOWNTO 0);
SIGNAL dp_offload_rx_10GbE_snk_in_arr : t_dp_sosi_arr(c_nof_streams_10GbE-1 DOWNTO 0);
......@@ -434,11 +464,26 @@ ARCHITECTURE str OF unb2c_test IS
SIGNAL ram_diag_data_buf_ddr_MB_II_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_ddr_MB_II_miso : t_mem_miso;
-- Interface: 1GbE UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_nof_streams_1GbE_UDP-1 DOWNTO 0);
-- UDP streaming ports for 1GbE I and 1GbE II
-- . 1GbE I
SIGNAL gn_eth_src_mac_I : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_I : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_I : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
SIGNAL eth1g_I_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
SIGNAL eth1g_I_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
SIGNAL eth1g_I_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0);
SIGNAL eth1g_I_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_I-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- . 1GbE II
SIGNAL gn_eth_src_mac_II : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
SIGNAL gn_ip_src_addr_II : STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
SIGNAL gn_udp_src_port_II : STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
SIGNAL eth1g_II_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
SIGNAL eth1g_II_udp_tx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
SIGNAL eth1g_II_udp_rx_sosi_arr : t_dp_sosi_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0);
SIGNAL eth1g_II_udp_rx_siso_arr : t_dp_siso_arr(c_nof_udp_streams_1GbE_II-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
......@@ -446,7 +491,10 @@ ARCHITECTURE str OF unb2c_test IS
BEGIN
ASSERT FALSE REPORT "g_design_name=" & g_design_name SEVERITY WARNING;
ASSERT FALSE REPORT "g_design_name = " & g_design_name SEVERITY NOTE;
gn_index <= TO_UINT(ID);
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
......@@ -463,8 +511,9 @@ BEGIN
g_mm_clk_freq => c_mm_clk_freq,
g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
g_aux => c_unb2c_board_aux,
g_base_ip => c_base_ip, -- = X"0A63" is base IP address used by unb_osy: 10.99.xx.yy
g_udp_offload => c_use_1GbE_I_UDP,
g_udp_offload_nof_streams => c_nof_streams_1GbE_UDP,
g_udp_offload_nof_streams => c_nof_udp_streams_1GbE_I,
g_factory_image => g_factory_image,
g_protect_addr_range => g_protect_addr_range
)
......@@ -484,7 +533,7 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => OPEN,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
......@@ -545,10 +594,10 @@ BEGIN
eth1g_ram_miso => eth1g_eth0_ram_miso,
-- eth1g UDP streaming ports
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
udp_rx_sosi_arr => eth1g_udp_rx_sosi_arr,
udp_rx_siso_arr => eth1g_udp_rx_siso_arr,
udp_tx_sosi_arr => eth1g_I_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_I_udp_tx_siso_arr,
udp_rx_sosi_arr => eth1g_I_udp_rx_sosi_arr,
udp_rx_siso_arr => eth1g_I_udp_rx_siso_arr,
-- scrap ram
ram_scrap_mosi => ram_scrap_mosi,
......@@ -761,89 +810,65 @@ BEGIN
ram_scrap_miso => ram_scrap_miso
);
-- TODO: Add support for second 1GbE port
gen_udp_stream_1GbE : IF c_use_1GbE_I_UDP = TRUE GENERATE
u_udp_stream_1GbE : ENTITY work.udp_stream
gn_eth_src_mac_I <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
gn_ip_src_addr_I <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 0);
gn_udp_src_port_I <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 0);
u_eth_tester_I : ENTITY eth_lib.eth_tester
GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology,
g_nof_streams => c_nof_streams_1GbE_UDP,
g_data_w => c_data_w_32,
g_bg_block_size => c_def_1GbE_block_size,
g_bg_gapsize => c_bg_gapsize_1GbE,
g_bg_blocks_per_sync => c_bg_blocks_per_sync,
g_def_block_size => c_def_1GbE_block_size,
g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet_1GbE,
g_remove_crc => TRUE
g_nof_streams => c_nof_udp_streams_1GbE_I,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => dp_rst,
st_clk => dp_clk,
st_pps => dp_pps,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- UDP transmit interface
eth_src_mac => gn_eth_src_mac_I,
ip_src_addr => gn_ip_src_addr_I,
udp_src_port => gn_udp_src_port_I,
ID => ID,
tx_fifo_rd_emp_arr => OPEN,
-- blockgen MM
reg_diag_bg_mosi => reg_diag_bg_1GbE_mosi,
reg_diag_bg_miso => reg_diag_bg_1GbE_miso,
ram_diag_bg_mosi => ram_diag_bg_1GbE_mosi,
ram_diag_bg_miso => ram_diag_bg_1GbE_miso,
reg_diag_tx_seq_mosi => reg_diag_tx_seq_1GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_1GbE_miso,
-- dp_offload_tx
-- reg_dp_offload_tx_mosi => reg_dp_offload_tx_1GbE_mosi,
-- reg_dp_offload_tx_miso => reg_dp_offload_tx_1GbE_miso,
-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_1GbE_hdr_dat_mosi,
-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_1GbE_hdr_dat_miso,
dp_offload_tx_src_out_arr => dp_offload_tx_1GbE_src_out_arr,
dp_offload_tx_src_in_arr => dp_offload_tx_1GbE_src_in_arr,
-- dp_offload_rx
-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_1GbE_hdr_dat_mosi,
-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_1GbE_hdr_dat_miso,
dp_offload_rx_snk_in_arr => dp_offload_rx_1GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_1GbE_snk_out_arr,
-- bsn
reg_bsn_monitor_mosi => reg_bsn_monitor_1GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_1GbE_miso,
-- databuffer
reg_diag_data_buf_mosi => reg_diag_data_buf_1GbE_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_1GbE_miso,
ram_diag_data_buf_mosi => ram_diag_data_buf_1GbE_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_1GbE_miso,
reg_diag_rx_seq_mosi => reg_diag_rx_seq_1GbE_mosi,
reg_diag_rx_seq_miso => reg_diag_rx_seq_1GbE_miso
tx_udp_sosi_arr => eth1g_I_udp_tx_sosi_arr,
tx_udp_siso_arr => eth1g_I_udp_tx_siso_arr,
-- UDP receive interface
rx_udp_sosi_arr => eth1g_I_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
reg_bg_ctrl_copi => reg_eth1g_I_bg_ctrl_copi,
reg_bg_ctrl_cipo => reg_eth1g_I_bg_ctrl_cipo,
reg_hdr_dat_copi => reg_eth1g_I_hdr_dat_copi,
reg_hdr_dat_cipo => reg_eth1g_I_hdr_dat_cipo,
reg_bsn_monitor_v2_tx_copi => reg_eth1g_I_bsn_monitor_v2_tx_copi,
reg_bsn_monitor_v2_tx_cipo => reg_eth1g_I_bsn_monitor_v2_tx_cipo,
reg_strobe_total_count_tx_copi => reg_eth1g_I_strobe_total_count_tx_copi,
reg_strobe_total_count_tx_cipo => reg_eth1g_I_strobe_total_count_tx_cipo,
-- . Rx
reg_bsn_monitor_v2_rx_copi => reg_eth1g_I_bsn_monitor_v2_rx_copi,
reg_bsn_monitor_v2_rx_cipo => reg_eth1g_I_bsn_monitor_v2_rx_cipo,
reg_strobe_total_count_rx_copi => reg_eth1g_I_strobe_total_count_rx_copi,
reg_strobe_total_count_rx_cipo => reg_eth1g_I_strobe_total_count_rx_cipo
);
END GENERATE;
-----------------------------------------------------------------------------
-- Interface : 1GbE
-----------------------------------------------------------------------------
-- TODO: Add support for second 1GbE port
gen_wires_1GbE : IF c_use_1GbE_I_UDP=TRUE GENERATE
gen_1GbE_wires : FOR i IN 0 TO c_nof_streams_1GbE_UDP-1 GENERATE
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
END GENERATE;
END GENERATE;
-- Instantiate a second 1G Eth to check pinning
gen_eth_II: IF c_use_1GbE_II=TRUE GENERATE
--gen_eth_II: IF FALSE GENERATE
-- Instantiate a second 1GbE to check pinning
gen_eth_II: IF c_use_1GbE_II = TRUE GENERATE
u_eth : ENTITY eth_lib.eth
GENERIC MAP (
g_technology => g_technology,
g_init_ip_address => C_base_ip_II & X"0000", -- Last two bytes set by board/FPGA ID.
g_init_ip_address => c_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
g_cross_clock_domain => TRUE,
g_frm_discard_en => TRUE
)
......@@ -879,6 +904,56 @@ BEGIN
-- LED interface
tse_led => open
);
-- TODO: Add control and connect for second 1GbE
gn_eth_src_mac_II <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 1);
gn_ip_src_addr_II <= c_base_ip & func_eth_tester_gn_index_to_ip_15_0(gn_index, 1);
gn_udp_src_port_II <= c_base_udp & func_eth_tester_gn_index_to_udp_7_0(gn_index, 1);
u_eth_tester_II : ENTITY eth_lib.eth_tester
GENERIC MAP (
g_nof_streams => c_nof_udp_streams_1GbE_II,
g_bg_sync_timeout => c_eth_tester_sync_timeout, -- BG sync interval < 11 s
g_remove_crc => TRUE -- use TRUE when using TSE link interface
)
PORT MAP (
-- Clocks and reset
mm_rst => mm_rst,
mm_clk => mm_clk,
st_rst => dp_rst,
st_clk => dp_clk,
st_pps => dp_pps,
-- UDP transmit interface
eth_src_mac => gn_eth_src_mac_II,
ip_src_addr => gn_ip_src_addr_II,
udp_src_port => gn_udp_src_port_II,
tx_fifo_rd_emp_arr => OPEN,
tx_udp_sosi_arr => eth1g_II_udp_tx_sosi_arr,
tx_udp_siso_arr => eth1g_II_udp_tx_siso_arr,
-- UDP receive interface
rx_udp_sosi_arr => eth1g_II_udp_rx_sosi_arr,
-- Memory Mapped Slaves (one per stream)
-- . Tx
reg_bg_ctrl_copi => reg_eth1g_II_bg_ctrl_copi,
reg_bg_ctrl_cipo => reg_eth1g_II_bg_ctrl_cipo,
reg_hdr_dat_copi => reg_eth1g_II_hdr_dat_copi,
reg_hdr_dat_cipo => reg_eth1g_II_hdr_dat_cipo,
reg_bsn_monitor_v2_tx_copi => reg_eth1g_II_bsn_monitor_v2_tx_copi,
reg_bsn_monitor_v2_tx_cipo => reg_eth1g_II_bsn_monitor_v2_tx_cipo,
reg_strobe_total_count_tx_copi => reg_eth1g_II_strobe_total_count_tx_copi,
reg_strobe_total_count_tx_cipo => reg_eth1g_II_strobe_total_count_tx_cipo,
-- . Rx
reg_bsn_monitor_v2_rx_copi => reg_eth1g_II_bsn_monitor_v2_rx_copi,
reg_bsn_monitor_v2_rx_cipo => reg_eth1g_II_bsn_monitor_v2_rx_cipo,
reg_strobe_total_count_rx_copi => reg_eth1g_II_strobe_total_count_rx_copi,
reg_strobe_total_count_rx_cipo => reg_eth1g_II_strobe_total_count_rx_cipo
);
END GENERATE;
......@@ -1031,7 +1106,6 @@ BEGIN
QSFP_5_TX <= i_QSFP_TX(5);
u_front_io : ENTITY unb2c_board_lib.unb2c_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => c_nof_qsfp_bus
......@@ -1103,7 +1177,6 @@ BEGIN
END GENERATE;
gen_back_wiring : IF c_use_10GbE_back0 = TRUE GENERATE
gen_back0_wires: FOR i IN 0 TO c_nof_streams_back0-1 GENERATE
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
......@@ -1389,6 +1462,4 @@ BEGIN
);
END GENERATE;
END str;
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