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Commit 3955f072 authored by Eric Kooistra's avatar Eric Kooistra
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Made tb self stopping using tb_end.

parent 1ad5e995
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...@@ -60,27 +60,28 @@ ARCHITECTURE tb OF tb_st_acc IS ...@@ -60,27 +60,28 @@ ARCHITECTURE tb OF tb_st_acc IS
RETURN TO_SVEC(v_result, g_acc_w); RETURN TO_SVEC(v_result, g_acc_w);
END; END;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '0'; SIGNAL clk : STD_LOGIC := '0';
SIGNAL in_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); SIGNAL in_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
SIGNAL in_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL in_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL in_val : STD_LOGIC; SIGNAL in_val : STD_LOGIC;
SIGNAL in_load : STD_LOGIC; SIGNAL in_load : STD_LOGIC;
SIGNAL out_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
SIGNAL out_val : STD_LOGIC; SIGNAL out_val : STD_LOGIC;
SIGNAL out_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
SIGNAL expected_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
SIGNAL expected_acc_p : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0); SIGNAL expected_acc_p : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
SIGNAL expected_acc : STD_LOGIC_VECTOR(g_acc_w-1 DOWNTO 0);
BEGIN BEGIN
clk <= NOT clk AFTER clk_period/2; clk <= NOT clk OR tb_end AFTER clk_period/2;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Input stimuli -- Input stimuli
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- run 10 us -- run -all
p_stimuli : PROCESS p_stimuli : PROCESS
BEGIN BEGIN
in_load <= '0'; in_load <= '0';
...@@ -107,6 +108,8 @@ BEGIN ...@@ -107,6 +108,8 @@ BEGIN
END LOOP; END LOOP;
in_load <= '1'; -- keep '1' to avoid further toggling of out_acc (in a real design this would safe power) in_load <= '1'; -- keep '1' to avoid further toggling of out_acc (in a real design this would safe power)
in_val <= '0'; in_val <= '0';
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
......
...@@ -44,8 +44,9 @@ ARCHITECTURE tb OF tb_st_calc IS ...@@ -44,8 +44,9 @@ ARCHITECTURE tb OF tb_st_calc IS
CONSTANT c_nof_accum_per_sync : NATURAL := 5; -- integration time CONSTANT c_nof_accum_per_sync : NATURAL := 5; -- integration time
SIGNAL rst : STD_LOGIC; SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL clk : STD_LOGIC := '0'; SIGNAL clk : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC;
SIGNAL in_sync : STD_LOGIC; SIGNAL in_sync : STD_LOGIC;
SIGNAL in_val : STD_LOGIC; SIGNAL in_val : STD_LOGIC;
...@@ -63,7 +64,7 @@ ARCHITECTURE tb OF tb_st_calc IS ...@@ -63,7 +64,7 @@ ARCHITECTURE tb OF tb_st_calc IS
BEGIN BEGIN
clk <= NOT clk AFTER clk_period/2; clk <= NOT clk OR tb_end AFTER clk_period/2;
in_a_re <= in_dat; in_a_re <= in_dat;
in_a_im <= in_dat; in_a_im <= in_dat;
...@@ -95,6 +96,8 @@ BEGIN ...@@ -95,6 +96,8 @@ BEGIN
FOR I IN 0 TO c_gap_size-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP; FOR I IN 0 TO c_gap_size-1 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
END LOOP; END LOOP;
END LOOP; END LOOP;
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(clk); END LOOP;
tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
......
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