Added ADC interface to OpenCL BSP

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml

@@ -31,6 +31,7 @@
     <interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
     <interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
     <interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
+    <interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
   </channels>
 
   <host>

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/flat.qsf

@@ -22,6 +22,7 @@ source ctrl_unb2_board.tcl
 source ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.tcl
 source ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
 source ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
+source ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
 #============================================================
 # Files and basic settings
 #============================================================
@@ -256,6 +257,11 @@ set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
 # internal termination should be enabled.
 set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
 
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+
 set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
 
 ### QSFP_0
@@ -460,6 +466,33 @@ set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
 set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
 set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
 
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                BCK_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to                BCK_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           BCK_RX[0]
+
+set_location_assignment PIN_BA7 -to BCK_RX[0]
+
+
+set_location_assignment PIN_V12 -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
+
+set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
+
+
 set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_40GbE.ip
 set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_10GbE.ip
 set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_1GbE_mc.ip
+set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_jesd204b.ip

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/freeze_wrapper.v

@@ -38,6 +38,9 @@ module freeze_wrapper(
   input [7:0]     board_kernel_cra_byteenable,
   input           board_kernel_cra_debugaccess,
 
+  input  wire [15:0]  board_kernel_stream_src_ADC_data,
+  input  wire         board_kernel_stream_src_ADC_valid,
+  output wire         board_kernel_stream_src_ADC_ready,
 
   input  wire [39:0]  board_kernel_stream_src_1GbE_data,
   input  wire         board_kernel_stream_src_1GbE_valid,
@@ -203,7 +206,9 @@ pr_region pr_region_inst
   .kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data),
   .kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready),
   .kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid),
-
+  .kernel_stream_src_ADC_data(board_kernel_stream_src_ADC_data),
+  .kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
+  .kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
   .kernel_register_mem_address(board_kernel_register_mem_address),  
   .kernel_register_mem_clken(board_kernel_register_mem_clken),  
   .kernel_register_mem_chipselect(board_kernel_register_mem_chipselect),  

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/pr_region.v

@@ -43,6 +43,10 @@ module pr_region (
   output  wire [255:0]  kernel_register_mem_writedata,  
   output  wire [31:0]   kernel_register_mem_byteenable, 
 
+  input  wire [15:0]  kernel_stream_src_ADC_data,
+  input  wire         kernel_stream_src_ADC_valid,
+  output wire         kernel_stream_src_ADC_ready,
+
   input  wire [39:0]  kernel_stream_src_1GbE_data,
   input  wire         kernel_stream_src_1GbE_valid,
   output wire         kernel_stream_src_1GbE_ready,
@@ -190,7 +194,12 @@ kernel_system kernel_system_inst
 
   .kernel_output_1GbE_data(kernel_stream_snk_1GbE_data),
   .kernel_output_1GbE_ready(kernel_stream_snk_1GbE_ready),
-  .kernel_output_1GbE_valid(kernel_stream_snk_1GbE_valid)
+  .kernel_output_1GbE_valid(kernel_stream_snk_1GbE_valid),
+
+  .kernel_input_ADC_data(kernel_stream_src_ADC_data),
+  .kernel_input_ADC_ready(kernel_stream_src_ADC_ready),
+  .kernel_input_ADC_valid(kernel_stream_src_ADC_valid)
+
 
 //  .kernel_mem0_address(pipelined_kernel_mem0_s0_address),
 //  .kernel_mem0_read(pipelined_kernel_mem0_s0_read),

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/hdllib.cfg

+hdl_lib_name = ta2_unb2b_jesd204b
+hdl_library_clause_name = ta2_unb2b_jesd204b_lib
+hdl_lib_uses_synth = common technology dp tech_jesd204b 
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+                     
+synth_files =
+  ta2_unb2b_jesd204b.vhd
+test_bench_files =     
+
+regression_test_vhdl = 
+    
+[modelsim_project_file]
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_files =
+    $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+    
+
+quartus_vhdl_files = 
+
+quartus_qip_files =

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl

+post_message "Running ta2_unb2b_jesd204b script"
+set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+#============================================================
+# Files and basic settings
+#============================================================
+
+# Local HDL files
+set_global_assignment -name VHDL_FILE ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+
+# All used HDL library *_lib.qip files in order, copied from ta2_unb2b_jesd204b.qsf in RadioHDL build directory. 
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/technology/technology_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_ram/ip_arria10_e1sg_ram_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_memory/tech_memory_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_fifo/ip_arria10_e1sg_fifo_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fifo/tech_fifo_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_ddio/ip_arria10_e1sg_ddio_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_iobuf/tech_iobuf_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tst/tst_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/common/common_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/mm/mm_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_mult/ip_arria10_mult_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_complex_mult_rtl/ip_arria10_complex_mult_rtl_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_mult_add4/ip_arria10_e1sg_mult_add4_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_mult_add2/ip_arria10_e1sg_mult_add2_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_mult/tech_mult_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/common_mult/common_mult_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/easics/easics_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/dp/dp_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_pll/tech_pll_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_jesd204b/ip_arria10_e1sg_jesd204b_lib.qip"
+set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_jesd204b/tech_jesd204b_lib.qip"

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2019
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author:
+-- . Reinier van der Walle
+-- Purpose:
+-- . Provide 10G ethernet I/O interface (BSP) for OpenCL kernel on Arria10
+-- Description:
+-- . This core consists of:
+--   . An Intel/Altera 10G Low Latency MAC instance
+--   . SOP/EOP insertion (kernel channel only carries data and valid)
+--   . Dual clock FIFO 
+--     . Clock domain transition between kernel_clk and clk_txmac
+--     . Buffers full Ethernet packet (10G MAC requires uninterrupted packet)
+--   . Clock (PLL) / reset generation
+-- . Details:
+--   . This core was developed for use on the Uniboard2b.
+--   .
+--   . The data field of the ST-avalon interface is also used to provide
+--   . SOP, EOP and empty meta-data. The implementation of this is shown below.
+--   +-----------+---------+--------------------------------------------------------+
+--   | Bit range | Name    | Description                                            |
+--   +-----------+---------+--------------------------------------------------------+
+--   | [0:15]    | payload | ADC channel 0 sample                                   |
+--   +-----------+---------+--------------------------------------------------------+
+LIBRARY IEEE, common_lib, dp_lib, tech_pll_lib, technology_lib, tech_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+
+ENTITY ta2_unb2b_jesd204b IS       
+  PORT (      
+    config_clk       : IN  STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+    config_reset     : IN  STD_LOGIC;
+
+    -- MM Control
+    jesd204b_mosi_address     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    jesd204b_mosi_wrdata      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    jesd204b_mosi_wr          : IN  STD_LOGIC;
+    jesd204b_mosi_rd          : IN  STD_LOGIC;
+    jesd204b_miso_rddata      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    jesd204b_miso_waitrequest : OUT STD_LOGIC;
+
+    -- JESD204B external signals
+    jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+    jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ 
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+    kernel_clk       : IN  STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+    kernel_reset     : IN  STD_LOGIC;
+
+    kernel_src_data  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- RX Data to kernel
+    kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
+    kernel_src_ready : IN  STD_LOGIC -- Flow control from kernel
+
+  );
+END ta2_unb2b_jesd204b;
+
+
+ARCHITECTURE str OF ta2_unb2b_jesd204b IS
+
+  CONSTANT c_sim                           : BOOLEAN := FALSE;
+
+  CONSTANT c_nof_streams_jesd204b          : NATURAL := 1;
+
+  CONSTANT c_rx_fifo_size                  : NATURAL := 32; -- should be large enough
+
+  SIGNAL dp_fifo_dc_rx_src_out             : t_dp_sosi; 
+  SIGNAL dp_fifo_dc_rx_snk_in              : t_dp_sosi := c_dp_sosi_rst; 
+  SIGNAL dp_fifo_dc_rx_src_in              : t_dp_siso;
+  SIGNAL dp_fifo_dc_rx_snk_out             : t_dp_siso;
+
+  SIGNAL dp_latency_adapter_rx_src_out     : t_dp_sosi; 
+  SIGNAL dp_latency_adapter_rx_src_in      : t_dp_siso;
+
+  SIGNAL jesd204b_rx_src_out_arr           : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_frame_clk                : STD_LOGIC;
+  SIGNAL jesd204b_rx_src_out_flat_w_sync   : t_dp_sosi;
+
+  SIGNAL jesd204b_mosi : t_mem_mosi;  
+  SIGNAL jesd204b_miso : t_mem_miso;
+
+BEGIN
+
+  jesd204b_mosi.address(7 DOWNTO 0)     <= jesd204b_mosi_address;
+  jesd204b_mosi.wrdata(31 DOWNTO 0)     <= jesd204b_mosi_wrdata;
+  jesd204b_mosi.wr          <= jesd204b_mosi_wr;
+  jesd204b_mosi.rd          <= jesd204b_mosi_rd;
+  jesd204b_miso_rddata      <= jesd204b_miso.rddata(31 DOWNTO 0);
+  jesd204b_miso_waitrequest <= jesd204b_miso.waitrequest;
+
+  u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
+  GENERIC MAP(
+    g_sim                => c_sim,                
+    g_nof_channels       => c_nof_streams_jesd204b    
+  )
+  PORT MAP(
+    jesd204b_refclk      => jesd204b_refclk,   
+    jesd204b_sysref      => jesd204b_sysref,   
+    jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
+  
+    rx_src_out_arr       => jesd204b_rx_src_out_arr,          
+    jesd204b_frame_clk   => jesd204b_frame_clk,          
+  
+    -- MM
+    mm_clk               => config_clk,           
+    mm_rst               => config_reset,           
+  
+    jesd204b_mosi        => jesd204b_mosi,         
+    jesd204b_miso        => jesd204b_miso,         
+  
+     -- Serial
+    serial_tx_arr        => open,
+    serial_rx_arr        => serial_rx_arr
+  );
+    
+
+  ---------------------------------------------------------------------------------------
+  -- RX FIFO: adc_clk -> kernel_clk
+  ---------------------------------------------------------------------------------------
+
+  dp_fifo_dc_rx_snk_in.data(13 DOWNTO 0) <= jesd204b_rx_src_out_arr(0).data(15 DOWNTO 2);
+  dp_fifo_dc_rx_snk_in.data(14) <= jesd204b_rx_src_out_arr(0).data(15);
+  dp_fifo_dc_rx_snk_in.data(15) <= jesd204b_rx_src_out_arr(0).data(15);
+  dp_fifo_dc_rx_snk_in.valid <= dp_fifo_dc_rx_snk_out.ready AND jesd204b_rx_src_out_arr(0).valid;
+
+  u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
+  GENERIC MAP (
+    g_technology  => c_tech_arria10_e1sg,
+    g_data_w      => 16,
+    g_empty_w     => 1,
+    g_use_empty   => FALSE,
+    g_use_ctrl    => FALSE,
+    g_fifo_size   => c_rx_fifo_size
+  )
+  PORT MAP (
+    wr_rst      => kernel_reset,
+    wr_clk      => jesd204b_frame_clk,
+    rd_rst      => kernel_reset,
+    rd_clk      => kernel_clk,
+  
+    snk_out     => dp_fifo_dc_rx_snk_out,
+    snk_in      => dp_fifo_dc_rx_snk_in,
+  
+    src_in      => dp_fifo_dc_rx_src_in, 
+    src_out     => dp_fifo_dc_rx_src_out
+  );   
+
+
+  ----------------------------------------------------------------------------
+  -- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
+  ----------------------------------------------------------------------------
+  u_dp_latency_adapter_rx : ENTITY dp_lib.dp_latency_adapter
+  GENERIC MAP (
+    g_in_latency  => 1,
+    g_out_latency => 0 
+  )
+  PORT MAP (
+    clk       => kernel_clk,
+    rst       => kernel_reset,
+
+    snk_in    => dp_fifo_dc_rx_src_out, 
+    snk_out   => dp_fifo_dc_rx_src_in, 
+
+    src_out   => dp_latency_adapter_rx_src_out, 
+    src_in    => dp_latency_adapter_rx_src_in 
+  );
+      
+
+  ----------------------------------------------------------------------------
+  -- Data mapping 
+  ----------------------------------------------------------------------------
+  -- Reverse byte order
+  --gen_rx_bytes: FOR I IN 0 TO c_halfword_sz-1 GENERATE
+  --  kernel_src_data(c_byte_w*(c_halfword_sz-I) -1  DOWNTO c_byte_w*(c_halfword_sz-1-I)) <= dp_latency_adapter_rx_src_out.data(c_byte_w*(I+1) -1 DOWNTO c_byte_w*I);
+  --END GENERATE;
+
+  kernel_src_data <= dp_latency_adapter_rx_src_out.data(15 DOWNTO 0);
+
+  kernel_src_valid <= dp_latency_adapter_rx_src_out.valid;
+  dp_latency_adapter_rx_src_in.ready <= kernel_src_ready;
+  dp_latency_adapter_rx_src_in.xon <= '1';
+
+
+END str;
+

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc_hw.tcl~ → applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_hw.tcl

 # TCL File Generated by Component Editor 18.0
-# Mon Jan 13 11:25:28 CET 2020
+# Wed Feb 12 15:16:50 CET 2020
 # DO NOT MODIFY
 
 
 # 
-# ta2_unb2b_1GbE_mc "ta2_unb2b_1GbE_mc" v1.0
-#  2020.01.13.11:25:28
+# ta2_unb2b_jesd204b "ta2_unb2b_jesd204b" v1.0
+#  2020.02.12.15:16:50
 # 
 # 
 
@@ -16,15 +16,15 @@ package require -exact qsys 18.0
 
 
 # 
-# module ta2_unb2b_1GbE_mc
+# module ta2_unb2b_jesd204b
 # 
 set_module_property DESCRIPTION ""
-set_module_property NAME ta2_unb2b_1GbE_mc
+set_module_property NAME ta2_unb2b_jesd204b
 set_module_property VERSION 1.0
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME ta2_unb2b_1GbE_mc
+set_module_property DISPLAY_NAME ta2_unb2b_jesd204b
 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 set_module_property EDITABLE true
 set_module_property REPORT_TO_TALKBACK false
@@ -36,10 +36,10 @@ set_module_property REPORT_HIERARCHY false
 # file sets
 # 
 add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_1GbE_mc_ip_wrapper
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL ta2_unb2b_jesd204b_ip_wrapper
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file ta2_unb2b_1GbE_mc_ip_wrapper.vhd VHDL PATH ta2_unb2b_1GbE_mc_ip_wrapper.vhd TOP_LEVEL_FILE
+add_fileset_file ta2_unb2b_jesd204b_ip_wrapper.vhd VHDL PATH ta2_unb2b_jesd204b_ip_wrapper.vhd TOP_LEVEL_FILE
 
 
 # 
@@ -52,29 +52,6 @@ add_fileset_file ta2_unb2b_1GbE_mc_ip_wrapper.vhd VHDL PATH ta2_unb2b_1GbE_mc_ip
 # 
 
 
-# 
-# connection point kernel_snk
-# 
-add_interface kernel_snk avalon_streaming end
-set_interface_property kernel_snk associatedClock kernel_clk
-set_interface_property kernel_snk associatedReset kernel_reset
-set_interface_property kernel_snk dataBitsPerSymbol 8
-set_interface_property kernel_snk errorDescriptor ""
-set_interface_property kernel_snk firstSymbolInHighOrderBits true
-set_interface_property kernel_snk maxChannel 0
-set_interface_property kernel_snk readyAllowance 0
-set_interface_property kernel_snk readyLatency 0
-set_interface_property kernel_snk ENABLED true
-set_interface_property kernel_snk EXPORT_OF ""
-set_interface_property kernel_snk PORT_NAME_MAP ""
-set_interface_property kernel_snk CMSIS_SVD_VARIABLES ""
-set_interface_property kernel_snk SVD_ADDRESS_GROUP ""
-
-add_interface_port kernel_snk kernel_snk_data data Input 40
-add_interface_port kernel_snk kernel_snk_ready ready Output 1
-add_interface_port kernel_snk kernel_snk_valid valid Input 1
-
-
 # 
 # connection point kernel_src
 # 
@@ -93,7 +70,7 @@ set_interface_property kernel_src PORT_NAME_MAP ""
 set_interface_property kernel_src CMSIS_SVD_VARIABLES ""
 set_interface_property kernel_src SVD_ADDRESS_GROUP ""
 
-add_interface_port kernel_src kernel_src_data data Output 40
+add_interface_port kernel_src kernel_src_data data Output 16
 add_interface_port kernel_src kernel_src_ready ready Input 1
 add_interface_port kernel_src kernel_src_valid valid Output 1
 
@@ -111,6 +88,20 @@ set_interface_property kernel_clk SVD_ADDRESS_GROUP ""
 add_interface_port kernel_clk kernel_clk clk Input 1
 
 
+# 
+# connection point config_reset
+# 
+add_interface config_reset reset end
+set_interface_property config_reset associatedClock ""
+set_interface_property config_reset synchronousEdges NONE
+set_interface_property config_reset ENABLED true
+set_interface_property config_reset EXPORT_OF ""
+set_interface_property config_reset PORT_NAME_MAP ""
+set_interface_property config_reset CMSIS_SVD_VARIABLES ""
+set_interface_property config_reset SVD_ADDRESS_GROUP ""
+
+add_interface_port config_reset config_reset reset Input 1
+
 
 # 
 # connection point kernel_reset
@@ -127,3 +118,119 @@ set_interface_property kernel_reset SVD_ADDRESS_GROUP ""
 add_interface_port kernel_reset kernel_reset reset Input 1
 
 
+# 
+# connection point mem
+# 
+add_interface mem avalon end
+set_interface_property mem addressGroup 0
+set_interface_property mem addressUnits WORDS
+set_interface_property mem associatedClock config_clk
+set_interface_property mem associatedReset config_reset
+set_interface_property mem bitsPerSymbol 8
+set_interface_property mem bridgedAddressOffset ""
+set_interface_property mem bridgesToMaster ""
+set_interface_property mem burstOnBurstBoundariesOnly false
+set_interface_property mem burstcountUnits WORDS
+set_interface_property mem explicitAddressSpan 0
+set_interface_property mem holdTime 0
+set_interface_property mem linewrapBursts false
+set_interface_property mem maximumPendingReadTransactions 0
+set_interface_property mem maximumPendingWriteTransactions 0
+set_interface_property mem minimumResponseLatency 1
+set_interface_property mem readLatency 1
+set_interface_property mem readWaitTime 1
+set_interface_property mem setupTime 0
+set_interface_property mem timingUnits Cycles
+set_interface_property mem transparentBridge false
+set_interface_property mem waitrequestAllowance 0
+set_interface_property mem writeWaitTime 0
+set_interface_property mem ENABLED true
+set_interface_property mem EXPORT_OF ""
+set_interface_property mem PORT_NAME_MAP ""
+set_interface_property mem CMSIS_SVD_VARIABLES ""
+set_interface_property mem SVD_ADDRESS_GROUP ""
+
+add_interface_port mem jesd204b_mosi_address address Input 8
+add_interface_port mem jesd204b_mosi_wrdata writedata Input 32
+add_interface_port mem jesd204b_mosi_wr write Input 1
+add_interface_port mem jesd204b_mosi_rd read Input 1
+add_interface_port mem jesd204b_miso_rddata readdata Output 32
+add_interface_port mem jesd204b_miso_waitrequest waitrequest Output 1
+set_interface_assignment mem embeddedsw.configuration.isFlash 0
+set_interface_assignment mem embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment mem embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment mem embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point config_clk
+# 
+add_interface config_clk clock end
+set_interface_property config_clk ENABLED true
+set_interface_property config_clk EXPORT_OF ""
+set_interface_property config_clk PORT_NAME_MAP ""
+set_interface_property config_clk CMSIS_SVD_VARIABLES ""
+set_interface_property config_clk SVD_ADDRESS_GROUP ""
+
+add_interface_port config_clk config_clk clk Input 1
+
+
+# 
+# connection point jesd204b_refclk
+# 
+add_interface jesd204b_refclk clock end
+set_interface_property jesd204b_refclk ENABLED true
+set_interface_property jesd204b_refclk EXPORT_OF ""
+set_interface_property jesd204b_refclk PORT_NAME_MAP ""
+set_interface_property jesd204b_refclk CMSIS_SVD_VARIABLES ""
+set_interface_property jesd204b_refclk SVD_ADDRESS_GROUP ""
+
+add_interface_port jesd204b_refclk jesd204b_refclk clk Input 1
+
+
+# 
+# connection point jesd204b_sysref
+# 
+add_interface jesd204b_sysref conduit end
+set_interface_property jesd204b_sysref associatedClock jesd204b_refclk
+set_interface_property jesd204b_sysref associatedReset kernel_reset
+set_interface_property jesd204b_sysref ENABLED true
+set_interface_property jesd204b_sysref EXPORT_OF ""
+set_interface_property jesd204b_sysref PORT_NAME_MAP ""
+set_interface_property jesd204b_sysref CMSIS_SVD_VARIABLES ""
+set_interface_property jesd204b_sysref SVD_ADDRESS_GROUP ""
+
+add_interface_port jesd204b_sysref jesd204b_sysref conduit Input 1
+
+
+# 
+# connection point jesd204b_sync_n
+# 
+add_interface jesd204b_sync_n conduit end
+set_interface_property jesd204b_sync_n associatedClock jesd204b_refclk
+set_interface_property jesd204b_sync_n associatedReset kernel_reset
+set_interface_property jesd204b_sync_n ENABLED true
+set_interface_property jesd204b_sync_n EXPORT_OF ""
+set_interface_property jesd204b_sync_n PORT_NAME_MAP ""
+set_interface_property jesd204b_sync_n CMSIS_SVD_VARIABLES ""
+set_interface_property jesd204b_sync_n SVD_ADDRESS_GROUP ""
+
+add_interface_port jesd204b_sync_n jesd204b_sync_n_arr conduit Output 1
+set_port_property jesd204b_sync_n_arr VHDL_TYPE STD_LOGIC_VECTOR
+
+
+# 
+# connection point serial_rx_arr
+# 
+add_interface serial_rx_arr conduit end
+set_interface_property serial_rx_arr associatedClock kernel_clk
+set_interface_property serial_rx_arr associatedReset kernel_reset
+set_interface_property serial_rx_arr ENABLED true
+set_interface_property serial_rx_arr EXPORT_OF ""
+set_interface_property serial_rx_arr PORT_NAME_MAP ""
+set_interface_property serial_rx_arr CMSIS_SVD_VARIABLES ""
+set_interface_property serial_rx_arr SVD_ADDRESS_GROUP ""
+
+add_interface_port serial_rx_arr serial_rx_arr conduit Input 1
+set_port_property serial_rx_arr VHDL_TYPE STD_LOGIC_VECTOR
+

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2019
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author:
+-- . Reinier van der Walle
+-- Purpose:
+-- . Instantiates ta2_unb2b_10GbE component 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ta2_unb2b_jesd204b_ip_wrapper IS       
+  PORT (      
+    config_clk       : IN  STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+    config_reset     : IN  STD_LOGIC;
+
+    -- MM Control
+    jesd204b_mosi_address     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+    jesd204b_mosi_wrdata      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+    jesd204b_mosi_wr          : IN  STD_LOGIC;
+    jesd204b_mosi_rd          : IN  STD_LOGIC;
+    jesd204b_miso_rddata      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    jesd204b_miso_waitrequest : OUT STD_LOGIC;
+
+    -- JESD204B external signals
+    jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+    jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ 
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+    kernel_clk       : IN  STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+    kernel_reset     : IN  STD_LOGIC;
+
+    kernel_src_data  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- RX Data to kernel
+    kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
+    kernel_src_ready : IN  STD_LOGIC -- Flow control from kernel
+
+  );
+END ta2_unb2b_jesd204b_ip_wrapper;
+
+
+ARCHITECTURE str OF ta2_unb2b_jesd204b_ip_wrapper IS
+  ----------------------------------------------------------------------------
+  -- ta2_unb2b_ Component
+  ----------------------------------------------------------------------------
+  COMPONENT ta2_unb2b_jesd204b IS       
+    PORT (      
+      config_clk       : IN  STD_LOGIC; -- 100MHz clk for reconfig block and status interface
+      config_reset     : IN  STD_LOGIC;
+  
+      -- MM Control
+      jesd204b_mosi_address     : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+      jesd204b_mosi_wrdata      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+      jesd204b_mosi_wr          : IN  STD_LOGIC;
+      jesd204b_mosi_rd          : IN  STD_LOGIC;
+      jesd204b_miso_rddata      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      jesd204b_miso_waitrequest : OUT STD_LOGIC;
+  
+      -- JESD204B external signals
+      jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
+      jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
+      jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+   
+      serial_rx_arr         : IN  STD_LOGIC_VECTOR(0 DOWNTO 0);
+  
+      kernel_clk       : IN  STD_LOGIC; -- Kernel clock (runs the kernel_* I/O below)
+      kernel_reset     : IN  STD_LOGIC;
+  
+      kernel_src_data  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- RX Data to kernel
+      kernel_src_valid : OUT STD_LOGIC; -- RX data valid signal to kernel
+      kernel_src_ready : IN  STD_LOGIC -- Flow control from kernel
+  
+    );
+  END COMPONENT ta2_unb2b_jesd204b;
+
+
+
+BEGIN
+
+  u_ta2_unb2b_jesd204b : ta2_unb2b_jesd204b
+    PORT MAP (      
+      config_clk                => config_clk, 
+      config_reset              => config_reset, 
+      jesd204b_mosi_address     => jesd204b_mosi_address,    
+      jesd204b_mosi_wrdata      => jesd204b_mosi_wrdata,     
+      jesd204b_mosi_wr          => jesd204b_mosi_wr,         
+      jesd204b_mosi_rd          => jesd204b_mosi_rd,         
+      jesd204b_miso_rddata      => jesd204b_miso_rddata,     
+      jesd204b_miso_waitrequest => jesd204b_miso_waitrequest,
+      jesd204b_refclk           => jesd204b_refclk,   
+      jesd204b_sysref           => jesd204b_sysref,    
+      jesd204b_sync_n_arr       => jesd204b_sync_n_arr,    
+      serial_rx_arr             => serial_rx_arr,   
+      kernel_clk                => kernel_clk,   
+      kernel_reset              => kernel_reset,    
+      kernel_src_data           => kernel_src_data,   
+      kernel_src_valid          => kernel_src_valid,    
+      kernel_src_ready          => kernel_src_ready       
+    );
+
+END str;
+

applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/top.vhd

@@ -79,6 +79,14 @@ ENTITY top IS
     QSFP_1_RX    : IN    STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
     QSFP_1_TX    : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
 
+     -- back transceivers
+    BCK_RX       : IN    STD_LOGIC_VECTOR(0 DOWNTO 0);
+    BCK_REF_CLK  : IN    STD_LOGIC; -- Use as JESD204B_REFCLK
+ 
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF : IN    STD_LOGIC;
+    JESD204B_SYNC   : OUT   STD_LOGIC_VECTOR(0 DOWNTO 0);
+
     -- LEDs
     QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
   );
@@ -244,6 +252,10 @@ ARCHITECTURE str OF top IS
   SIGNAL board_kernel_stream_snk_1GbE_valid          : std_logic; 
   SIGNAL board_kernel_stream_snk_1GbE_ready          : std_logic;
 
+  SIGNAL board_kernel_stream_src_ADC_data           : std_logic_vector(15 downto 0); 
+  SIGNAL board_kernel_stream_src_ADC_valid          : std_logic; 
+  SIGNAL board_kernel_stream_src_ADC_ready          : std_logic; 
+
   component board is
     port (
       avs_eth_0_clk_export                   : out std_logic;                                        -- export
@@ -430,7 +442,16 @@ ARCHITECTURE str OF top IS
       ta2_unb2b_1gbe_mc_udp_tx_src_out_endofpacket   : out std_logic;                                         -- endofpacket
       ta2_unb2b_1gbe_mc_udp_tx_src_out_startofpacket : out std_logic;                                         -- startofpacket
       ta2_unb2b_1gbe_mc_udp_tx_src_out_valid         : out std_logic;                                         -- valid
-      ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon       : in  std_logic                      := 'X'              -- xon
+      ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon       : in  std_logic                      := 'X';             -- xon
+
+      ta2_unb2b_jesd204b_kernel_src_data             : out std_logic_vector(15 downto 0);                     -- data
+      ta2_unb2b_jesd204b_kernel_src_ready            : in  std_logic                      := 'X';             -- ready
+      ta2_unb2b_jesd204b_kernel_src_valid            : out std_logic;                                         -- valid
+      ta2_unb2b_jesd204b_jesd204b_refclk_clk         : in  std_logic                      := 'X';             -- clk
+      ta2_unb2b_jesd204b_jesd204b_sysref_conduit     : in  std_logic                      := 'X';             -- conduit
+      ta2_unb2b_jesd204b_jesd204b_sync_n_conduit     : out std_logic_vector(0 downto 0);                      -- conduit
+      ta2_unb2b_jesd204b_serial_rx_arr_conduit       : in  std_logic_vector(0 downto 0)   := (others => 'X')  -- conduit
+
     );
   end component board;
 
@@ -478,8 +499,11 @@ ARCHITECTURE str OF top IS
       board_kernel_stream_src_1GbE_ready  : out std_logic; 
       board_kernel_stream_snk_1GbE_data   : out std_logic_vector(39 downto 0); 
       board_kernel_stream_snk_1GbE_valid  : out std_logic; 
-      board_kernel_stream_snk_1GbE_ready  : in  std_logic
-
+      board_kernel_stream_snk_1GbE_ready  : in  std_logic;
+                                          
+      board_kernel_stream_src_ADC_data   : in  std_logic_vector(15 downto 0); 
+      board_kernel_stream_src_ADC_valid  : in  std_logic; 
+      board_kernel_stream_src_ADC_ready  : out std_logic 
 
    );
   end component freeze_wrapper;
@@ -858,7 +882,17 @@ BEGIN
       ta2_unb2b_1gbe_mc_udp_tx_src_out_startofpacket => eth1g_udp_tx_sosi_arr(0).sop, 
       ta2_unb2b_1gbe_mc_udp_tx_src_out_valid         => eth1g_udp_tx_sosi_arr(0).valid, 
       ta2_unb2b_1gbe_mc_udp_tx_src_out_ready         => eth1g_udp_tx_siso_arr(0).ready, 
-      ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon       => eth1g_udp_tx_siso_arr(0).xon
+      ta2_unb2b_1gbe_mc_udp_tx_src_out_xon_xon       => eth1g_udp_tx_siso_arr(0).xon,
+
+      ta2_unb2b_jesd204b_kernel_src_data             => board_kernel_stream_src_ADC_data,  
+      ta2_unb2b_jesd204b_kernel_src_ready            => board_kernel_stream_src_ADC_ready,
+      ta2_unb2b_jesd204b_kernel_src_valid            => board_kernel_stream_src_ADC_valid,
+      ta2_unb2b_jesd204b_jesd204b_refclk_clk         => BCK_REF_CLK, 
+      ta2_unb2b_jesd204b_jesd204b_sysref_conduit     => JESD204B_SYSREF,
+      ta2_unb2b_jesd204b_jesd204b_sync_n_conduit     => JESD204B_SYNC,
+      ta2_unb2b_jesd204b_serial_rx_arr_conduit       => BCK_RX
+
+
   );
 
   -----------------------------------------------------------------------------
@@ -907,7 +941,12 @@ BEGIN
     board_kernel_stream_src_1GbE_ready   => board_kernel_stream_src_1GbE_ready,
     board_kernel_stream_snk_1GbE_data    => board_kernel_stream_snk_1GbE_data,
     board_kernel_stream_snk_1GbE_valid   => board_kernel_stream_snk_1GbE_valid,
-    board_kernel_stream_snk_1GbE_ready   => board_kernel_stream_snk_1GbE_ready
+    board_kernel_stream_snk_1GbE_ready   => board_kernel_stream_snk_1GbE_ready,
+
+    board_kernel_stream_src_ADC_data    => board_kernel_stream_src_ADC_data,
+    board_kernel_stream_src_ADC_valid   => board_kernel_stream_src_ADC_valid,
+    board_kernel_stream_src_ADC_ready   => board_kernel_stream_src_ADC_ready
+
   );