Merge branch 'master' of git.astron.nl:desp/hdl

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd

@@ -86,9 +86,9 @@ ENTITY node_adc_input_and_timing IS
     reg_bsn_monitor_input_miso     : OUT t_mem_miso;
 
     -- Data buffer for raw samples
-    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
     ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
-    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi := c_mem_mosi_rst;
     reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
 
     -- Data buffer for framed samples (variable depth)

applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg

@@ -19,6 +19,7 @@ synth_files =
     src/vhdl/lofar2_unb2b_sdp_station.vhd
     
 test_bench_files = 
+    tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
 
 regression_test_vhdl =
 

applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml

@@ -132,14 +132,14 @@ peripherals:
     parameter_overrides:
       - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
-      - REG_DIAG_WG
-      - RAM_DIAG_WG
+      - REG_WG
+      - RAM_WG
       
   - peripheral_name: aduh/aduh_mon_dc_power
     parameter_overrides:
       - { name: g_nof_streams, value: c_S_pn }
     mm_port_names:
-      - REG_ADUH_MON
+      - REG_ADUH_MONITOR
 
   # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
   #- peripheral_name: aduh/aduh_mon_data_buffer
@@ -198,7 +198,7 @@ peripherals:
   - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
     peripheral_group: sst
     mm_port_names:
-      - REG_STAT_HDR_INFO
+      - REG_STAT_HDR_DAT
 
   #############################################################################
   # BF = Beamformer (from node_sdp_beamformer.vhd)

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg

@@ -89,5 +89,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg

@@ -95,5 +95,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg

@@ -94,5 +94,7 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd

@@ -112,6 +112,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
   CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
   CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
   CONSTANT c_mm_file_ram_st_sst           : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+  CONSTANT c_mm_file_reg_stat_enable      : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+  CONSTANT c_mm_file_reg_stat_hdr_info    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
 
   -- Tb
   SIGNAL tb_end              : STD_LOGIC := '0';
@@ -287,6 +289,11 @@ BEGIN
                             "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3,   -- this is the wait until condition
                             c_sdp_T_sub, tb_clk);
 
+    ----------------------------------------------------------------------------
+    -- Offload enable
+    ----------------------------------------------------------------------------
+    mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+
     ---------------------------------------------------------------------------
     -- Read subband statistics
     ---------------------------------------------------------------------------

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd

@@ -26,7 +26,7 @@
 --   Unb2b version for lab testing
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, wpfb_lib, lofar2_sdp_lib, tech_pll_lib, nw_10gbe_lib, eth_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -41,6 +41,8 @@ USE dp_lib.dp_stream_pkg.ALL;
 USE wpfb_lib.wpfb_pkg.ALL;
 USE lofar2_sdp_lib.sdp_pkg.ALL;
 USE work.lofar2_unb2b_sdp_station_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
 
 ENTITY lofar2_unb2b_sdp_station IS
   GENERIC (
@@ -55,7 +57,7 @@ ENTITY lofar2_unb2b_sdp_station IS
     g_revision_id            : STRING  := "";  -- revision ID     -- set by QSF
     g_factory_image          : BOOLEAN := FALSE;
     g_protect_addr_range     : BOOLEAN := FALSE;
-    g_wpfb                   : t_wpfb := c_sdp_wpfb_subbands;
+    g_wpfb                   : t_wpfb  := c_sdp_wpfb_subbands;
     g_bsn_nof_clk_per_sync   : NATURAL := c_sdp_f_adc_MHz*10**6;  -- Default 200M, overide for short simulation 
     g_scope_selected_subband : NATURAL := 0
   );
@@ -132,11 +134,14 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   CONSTANT c_addr_w_reg_hdr_dat    : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w)); 
   CONSTANT c_addr_w_reg_dp_xonoff  : NATURAL := 1; 
   CONSTANT c_addr_w_ram_st_bst     : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+  
+  -- 
+  CONSTANT c_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
 
   -- Read only sdp_info values
   CONSTANT c_f_adc     : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
   CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
- 
+  
   SIGNAL gn_id    : STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
   SIGNAL gn_index : NATURAL := 0;
 
@@ -328,6 +333,21 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
   SIGNAL ram_st_bst_mosi_arr        : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
   SIGNAL ram_st_bst_miso_arr        : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
 
+  ----------------------------------------------
+  -- SST 
+  ----------------------------------------------
+  -- Statistics Enable
+  SIGNAL reg_stat_enable_mosi       : t_mem_mosi;
+  SIGNAL reg_stat_enable_miso       : t_mem_miso;
+  
+  -- Statistics header info  
+  SIGNAL reg_stat_hdr_dat_mosi      : t_mem_mosi;
+  SIGNAL reg_stat_hdr_dat_miso      : t_mem_miso;
+
+  -- Statistics
+  SIGNAL udp_tx_sosi_arr            : t_dp_sosi_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL udp_tx_siso_arr            : t_dp_siso_arr(c_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);  
+
   ----------------------------------------------
   -- 10 GbE 
   ----------------------------------------------
@@ -394,21 +414,23 @@ BEGIN
   -----------------------------------------------------------------------------
   u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
   GENERIC MAP (
-    g_sim                => g_sim,
-    g_technology         => g_technology,
-    g_design_name        => g_design_name,
-    g_design_note        => g_design_note,
-    g_stamp_date         => g_stamp_date,
-    g_stamp_time         => g_stamp_time, 
-    g_revision_id        => g_revision_id, 
-    g_fw_version         => c_fw_version,
-    g_mm_clk_freq        => c_mm_clk_freq,
-    g_eth_clk_freq       => c_unb2b_board_eth_clk_freq_125M,
-    g_aux                => c_unb2b_board_aux,
-    g_factory_image      => g_factory_image,
-    g_protect_addr_range => g_protect_addr_range,
-    g_dp_clk_freq        => c_unb2b_board_ext_clk_freq_200M,
-    g_dp_clk_use_pll     => FALSE
+    g_sim                     => g_sim,
+    g_technology              => g_technology,
+    g_design_name             => g_design_name,
+    g_design_note             => g_design_note,
+    g_stamp_date              => g_stamp_date,
+    g_stamp_time              => g_stamp_time, 
+    g_revision_id             => g_revision_id, 
+    g_fw_version              => c_fw_version,
+    g_mm_clk_freq             => c_mm_clk_freq,
+    g_eth_clk_freq            => c_unb2b_board_eth_clk_freq_125M,
+    g_aux                     => c_unb2b_board_aux,
+    g_factory_image           => g_factory_image,
+    g_protect_addr_range      => g_protect_addr_range,
+    g_dp_clk_freq             => c_unb2b_board_ext_clk_freq_200M,
+    g_dp_clk_use_pll          => FALSE,
+    g_udp_offload             => TRUE,
+    g_udp_offload_nof_streams => c_eth_nof_udp_ports
   )
   PORT MAP (
     -- Clock an reset signals
@@ -490,6 +512,10 @@ BEGIN
     eth1g_ram_mosi           => eth1g_ram_mosi,
     eth1g_ram_miso           => eth1g_ram_miso,
  
+    -- eth1g UDP streaming
+    udp_tx_sosi_arr          => udp_tx_sosi_arr,
+    udp_tx_siso_arr          => udp_tx_siso_arr,
+
     ram_scrap_mosi           => ram_scrap_mosi,
     ram_scrap_miso           => ram_scrap_miso,
    
@@ -535,42 +561,42 @@ BEGIN
     pout_wdi                 => pout_wdi,
 
     -- mm interfaces for control
-    reg_wdi_mosi             => reg_wdi_mosi,
-    reg_wdi_miso             => reg_wdi_miso,
-    reg_unb_system_info_mosi => reg_unb_system_info_mosi,
-    reg_unb_system_info_miso => reg_unb_system_info_miso,
-    rom_unb_system_info_mosi => rom_unb_system_info_mosi,
-    rom_unb_system_info_miso => rom_unb_system_info_miso, 
-    reg_unb_sens_mosi        => reg_unb_sens_mosi,
-    reg_unb_sens_miso        => reg_unb_sens_miso, 
-    reg_unb_pmbus_mosi       => reg_unb_pmbus_mosi,
-    reg_unb_pmbus_miso       => reg_unb_pmbus_miso,
-    reg_fpga_temp_sens_mosi  => reg_fpga_temp_sens_mosi,
-    reg_fpga_temp_sens_miso  => reg_fpga_temp_sens_miso,
+    reg_wdi_mosi                => reg_wdi_mosi,
+    reg_wdi_miso                => reg_wdi_miso,
+    reg_unb_system_info_mosi    => reg_unb_system_info_mosi,
+    reg_unb_system_info_miso    => reg_unb_system_info_miso,
+    rom_unb_system_info_mosi    => rom_unb_system_info_mosi,
+    rom_unb_system_info_miso    => rom_unb_system_info_miso, 
+    reg_unb_sens_mosi           => reg_unb_sens_mosi,
+    reg_unb_sens_miso           => reg_unb_sens_miso, 
+    reg_unb_pmbus_mosi          => reg_unb_pmbus_mosi,
+    reg_unb_pmbus_miso          => reg_unb_pmbus_miso,
+    reg_fpga_temp_sens_mosi     => reg_fpga_temp_sens_mosi,
+    reg_fpga_temp_sens_miso     => reg_fpga_temp_sens_miso,
     reg_fpga_voltage_sens_mosi  => reg_fpga_voltage_sens_mosi,
     reg_fpga_voltage_sens_miso  => reg_fpga_voltage_sens_miso,
-    reg_ppsh_mosi            => reg_ppsh_mosi,
-    reg_ppsh_miso            => reg_ppsh_miso, 
-    eth1g_mm_rst             => eth1g_mm_rst,
-    eth1g_tse_mosi           => eth1g_tse_mosi,
-    eth1g_tse_miso           => eth1g_tse_miso,
-    eth1g_reg_mosi           => eth1g_reg_mosi,
-    eth1g_reg_miso           => eth1g_reg_miso,
-    eth1g_reg_interrupt      => eth1g_reg_interrupt,
-    eth1g_ram_mosi           => eth1g_ram_mosi,
-    eth1g_ram_miso           => eth1g_ram_miso,
-    reg_dpmm_data_mosi       => reg_dpmm_data_mosi,
-    reg_dpmm_data_miso       => reg_dpmm_data_miso,
-    reg_dpmm_ctrl_mosi       => reg_dpmm_ctrl_mosi,
-    reg_dpmm_ctrl_miso       => reg_dpmm_ctrl_miso,
-    reg_mmdp_data_mosi       => reg_mmdp_data_mosi,
-    reg_mmdp_data_miso       => reg_mmdp_data_miso,
-    reg_mmdp_ctrl_mosi       => reg_mmdp_ctrl_mosi,
-    reg_mmdp_ctrl_miso       => reg_mmdp_ctrl_miso,
-    reg_epcs_mosi            => reg_epcs_mosi,
-    reg_epcs_miso            => reg_epcs_miso,
-    reg_remu_mosi            => reg_remu_mosi,
-    reg_remu_miso            => reg_remu_miso,
+    reg_ppsh_mosi               => reg_ppsh_mosi,
+    reg_ppsh_miso               => reg_ppsh_miso, 
+    eth1g_mm_rst                => eth1g_mm_rst,
+    eth1g_tse_mosi              => eth1g_tse_mosi,
+    eth1g_tse_miso              => eth1g_tse_miso,
+    eth1g_reg_mosi              => eth1g_reg_mosi,
+    eth1g_reg_miso              => eth1g_reg_miso,
+    eth1g_reg_interrupt         => eth1g_reg_interrupt,
+    eth1g_ram_mosi              => eth1g_ram_mosi,
+    eth1g_ram_miso              => eth1g_ram_miso,
+    reg_dpmm_data_mosi          => reg_dpmm_data_mosi,
+    reg_dpmm_data_miso          => reg_dpmm_data_miso,
+    reg_dpmm_ctrl_mosi          => reg_dpmm_ctrl_mosi,
+    reg_dpmm_ctrl_miso          => reg_dpmm_ctrl_miso,
+    reg_mmdp_data_mosi          => reg_mmdp_data_mosi,
+    reg_mmdp_data_miso          => reg_mmdp_data_miso,
+    reg_mmdp_ctrl_mosi          => reg_mmdp_ctrl_mosi,
+    reg_mmdp_ctrl_miso          => reg_mmdp_ctrl_miso,
+    reg_epcs_mosi               => reg_epcs_mosi,
+    reg_epcs_miso               => reg_epcs_miso,
+    reg_remu_mosi               => reg_remu_mosi,
+    reg_remu_miso               => reg_remu_miso,
 
     -- mm buses for signal flow blocks
     -- Jesd ip status/control
@@ -625,7 +651,11 @@ BEGIN
     reg_nw_10GbE_eth10g_mosi    => reg_nw_10GbE_eth10g_mosi,   
     reg_nw_10GbE_eth10g_miso    => reg_nw_10GbE_eth10g_miso,   
     ram_scrap_mosi              => ram_scrap_mosi,
-    ram_scrap_miso              => ram_scrap_miso   
+    ram_scrap_miso              => ram_scrap_miso,
+    reg_stat_enable_mosi        => reg_stat_enable_mosi,
+    reg_stat_enable_miso        => reg_stat_enable_miso,
+    reg_stat_hdr_dat_mosi       => reg_stat_hdr_dat_mosi,
+    reg_stat_hdr_dat_miso       => reg_stat_hdr_dat_miso   
   );
 
   -----------------------------------------------------------------------------
@@ -637,6 +667,7 @@ BEGIN
   cep_eth_src_mac  <= c_sdp_cep_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
   cep_ip_src_addr  <= c_sdp_cep_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
   cep_udp_src_port <= c_sdp_cep_udp_src_port_15_8 & ID;
+  
   stat_eth_src_mac <= c_sdp_stat_eth_src_mac_47_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & RESIZE_UVEC(this_chip_id, c_byte_w); -- Simply use chip_id since we only use 1 of the 6*4 = 24 10GbE port.
   stat_ip_src_addr <= c_sdp_stat_ip_src_addr_31_16 & RESIZE_UVEC(this_bck_id, c_byte_w) & INCR_UVEC(RESIZE_UVEC(this_chip_id, c_byte_w), 1); -- +1 to avoid IP = *.*.*.0
   sst_udp_src_port <= c_sdp_sst_udp_src_port_15_8 & ID;
@@ -732,6 +763,9 @@ BEGIN
       in_sosi_arr        => ait_sosi_arr,    
       pfb_sosi_arr       => pfb_sosi_arr,
       fsub_sosi_arr      => fsub_sosi_arr,
+
+      sst_udp_sosi       => udp_tx_sosi_arr(0),
+      sst_udp_siso       => udp_tx_siso_arr(0),
                                               
       mm_rst             => mm_rst, 
       mm_clk             => mm_clk, 
@@ -746,6 +780,11 @@ BEGIN
       ram_gains_miso     => ram_equalizer_gains_miso,     
       reg_selector_mosi  => reg_dp_selector_mosi,  
       reg_selector_miso  => reg_dp_selector_miso,
+
+      reg_enable_mosi    => reg_stat_enable_mosi,
+      reg_enable_miso    => reg_stat_enable_miso,
+      reg_hdr_dat_mosi   => reg_stat_hdr_dat_mosi,
+      reg_hdr_dat_miso   => reg_stat_hdr_dat_miso,
   
       sdp_info           => sdp_info,
       gn_id              => gn_id,

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd

@@ -182,6 +182,14 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
    ram_st_bst_mosi                : OUT t_mem_mosi;
    ram_st_bst_miso                : IN  t_mem_miso;
 
+   -- Subband Statistics (SST)
+   reg_stat_enable_mosi           : OUT t_mem_mosi;
+   reg_stat_enable_miso           : IN  t_mem_miso;
+
+   -- Statistics header info
+   reg_stat_hdr_dat_mosi          : OUT t_mem_mosi;
+   reg_stat_hdr_dat_miso          : IN  t_mem_miso;
+
    -- 10 GbE mac
    reg_nw_10GbE_mac_mosi          : OUT t_mem_mosi;
    reg_nw_10GbE_mac_miso          : IN  t_mem_miso;
@@ -306,6 +314,12 @@ BEGIN
 
     u_mm_file_ram_st_bst             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
                                               PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+    
+    u_mm_file_reg_stat_enable        : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE")
+                                               PORT MAP(mm_rst, mm_clk, reg_stat_enable_mosi, reg_stat_enable_miso );
+
+    u_mm_file_reg_stat_hdr_info      : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT")
+                                               PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_mosi, reg_stat_hdr_dat_miso);
 
     u_mm_file_reg_nw_10GbE_mac       : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
                                               PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
@@ -659,6 +673,22 @@ BEGIN
       ram_st_bst_read_export                    => ram_st_bst_mosi.rd,
       ram_st_bst_readdata_export                => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
 
+      reg_stat_enable_clk_export                => OPEN,
+      reg_stat_enable_reset_export              => OPEN,
+      reg_stat_enable_address_export            => reg_stat_enable_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+      reg_stat_enable_write_export              => reg_stat_enable_mosi.wr,
+      reg_stat_enable_writedata_export          => reg_stat_enable_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_enable_read_export               => reg_stat_enable_mosi.rd,
+      reg_stat_enable_readdata_export           => reg_stat_enable_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_stat_hdr_dat_clk_export                => OPEN,
+      reg_stat_hdr_dat_reset_export              => OPEN,
+      reg_stat_hdr_dat_address_export            => reg_stat_hdr_dat_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+      reg_stat_hdr_dat_write_export              => reg_stat_hdr_dat_mosi.wr,
+      reg_stat_hdr_dat_writedata_export          => reg_stat_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0), 
+      reg_stat_hdr_dat_read_export               => reg_stat_hdr_dat_mosi.rd,
+      reg_stat_hdr_dat_readdata_export           => reg_stat_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+
       reg_nw_10GbE_mac_clk_export               => OPEN,
       reg_nw_10GbE_mac_reset_export             => OPEN,
       reg_nw_10GbE_mac_address_export           => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),

applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd

@@ -287,6 +287,20 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
             reg_sdp_info_reset_export                 : out std_logic;                                        -- export
             reg_sdp_info_write_export                 : out std_logic;                                        -- export
             reg_sdp_info_writedata_export             : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_enable_address_export            : out std_logic_vector(0 downto 0);                     -- export
+            reg_stat_enable_clk_export                : out std_logic;                                        -- export
+            reg_stat_enable_read_export               : out std_logic;                                        -- export
+            reg_stat_enable_readdata_export           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_enable_reset_export              : out std_logic;                                        -- export
+            reg_stat_enable_write_export              : out std_logic;                                        -- export
+            reg_stat_enable_writedata_export          : out std_logic_vector(31 downto 0);                    -- export
+            reg_stat_hdr_dat_address_export           : out std_logic_vector(5 downto 0);                     -- export
+            reg_stat_hdr_dat_clk_export               : out std_logic;                                        -- export
+            reg_stat_hdr_dat_read_export              : out std_logic;                                        -- export
+            reg_stat_hdr_dat_readdata_export          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_stat_hdr_dat_reset_export             : out std_logic;                                        -- export
+            reg_stat_hdr_dat_write_export             : out std_logic;                                        -- export
+            reg_stat_hdr_dat_writedata_export         : out std_logic_vector(31 downto 0);                    -- export
             reg_si_address_export                     : out std_logic_vector(0 downto 0);                     -- export
             reg_si_clk_export                         : out std_logic;                                        -- export
             reg_si_read_export                        : out std_logic;                                        -- export

applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+-- Test statistics offload with "ethernet packet statistics" in wave window only
+-- Usage:
+--   > as 7    # default
+--   > as 12   # for detailed debugging
+--   > run -a  
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, eth_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_sdp_station IS
+END tb_lofar2_unb2b_sdp_station;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station IS
+
+  CONSTANT c_sim                          : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr                       : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr                      : NATURAL := 0;
+  CONSTANT c_id                           : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version                      : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+
+  CONSTANT c_eth_clk_period               : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period               : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period           : TIME := 5 ns;
+  CONSTANT c_pps_period                   : NATURAL := 1000;
+
+  CONSTANT c_tb_clk_period                : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+  CONSTANT c_nof_block_per_pps           : NATURAL := 16;
+  CONSTANT c_wpfb_sim                     : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_pps);
+   
+  -- WG
+  CONSTANT c_full_scale_ampl              : REAL := REAL(2**(18-1) - 1);  -- = full scale of WG
+  CONSTANT c_bsn_start_wg                 : NATURAL := 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+  CONSTANT c_ampl_sp_0                    : NATURAL := 2**(c_sdp_W_adc-1) / 2;  -- in number of lsb
+  CONSTANT c_wg_subband_freq_unit         : REAL := c_diag_wg_freq_unit / REAL(c_sdp_N_fft);  -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+  CONSTANT c_wg_freq_offset               : REAL := 0.0 / 11.0; -- in freq_unit
+  CONSTANT c_subband_sp_0                 : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+  CONSTANT c_wg_ampl_lsb                  : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
+
+-- . 1GbE output
+  CONSTANT c_eth_check_nof_packets        : NATURAL := 4512;  -- received packets in 2 sync periods
+  CONSTANT c_eth_runtime_timeout          : TIME := 100 ms;  -- factor 2 margin
+  
+  -- MM  
+  CONSTANT c_mm_file_reg_bsn_source_v2    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+  CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+  CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+
+  -- Tb
+  SIGNAL tb_end               : STD_LOGIC := '0';
+  SIGNAL sim_done             : STD_LOGIC := '0';
+  SIGNAL eth_done             : STD_LOGIC := '0';
+  SIGNAL verify_done          : STD_LOGIC := '0';
+  SIGNAL tb_clk               : STD_LOGIC := '0';
+
+  -- WG
+  SIGNAL current_bsn_wg       : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+  -- DUT
+  SIGNAL ext_clk              : STD_LOGIC := '0';
+  SIGNAL pps                  : STD_LOGIC := '0';
+  SIGNAL ext_pps              : STD_LOGIC := '0';
+  SIGNAL pps_rst              : STD_LOGIC := '0';
+
+  SIGNAL WDI                  : STD_LOGIC;
+  SIGNAL INTA                 : STD_LOGIC;
+  SIGNAL INTB                 : STD_LOGIC;
+
+  SIGNAL eth_clk              : STD_LOGIC := '0';
+  SIGNAL eth_txp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl             : STD_LOGIC;
+  SIGNAL sens_sda             : STD_LOGIC;
+  SIGNAL pmbus_scl            : STD_LOGIC;
+  SIGNAL pmbus_sda            : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK      : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref      : STD_LOGIC;
+  SIGNAL jesd204b_sync_n      : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+
+BEGIN
+
+  -- System setup
+  ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl  <= 'H';  -- pull up
+  sens_sda  <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  -- External PPS
+  proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+  ext_pps <= pps;
+
+  -- >> DUT <<
+  u_lofar_unb2b_sdp_station : ENTITY work.lofar2_unb2b_sdp_station
+  GENERIC MAP (
+    g_design_name            => "lofar2_unb2b_sdp_station_bf",
+    g_design_note            => "",
+    g_sim                    => c_sim,
+    g_sim_unb_nr             => c_unb_nr,
+    g_sim_node_nr            => c_node_nr,
+    g_wpfb                   => c_wpfb_sim,
+    g_scope_selected_subband => NATURAL(c_subband_sp_0)
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK                  => ext_clk,
+    PPS                  => pps,
+    WDI                  => WDI,
+    INTA                 => INTA,
+    INTB                 => INTB,
+
+    -- Others
+    VERSION              => c_version,
+    ID                   => c_id,
+    TESTIO               => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC              => sens_scl,
+    SENS_SD              => sens_sda,
+
+    PMBUS_SC             => pmbus_scl,
+    PMBUS_SD             => pmbus_sda,
+    PMBUS_ALERT          => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK              => eth_clk,
+    ETH_SGIN             => eth_rxp,
+    ETH_SGOUT            => eth_txp,
+
+    -- LEDs
+    QSFP_LED             => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK      => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF      => jesd204b_sysref,
+    JESD204B_SYNC_N      => jesd204b_sync_n
+  );
+
+  ---------------------------------------------------------------------------------------------------------------------
+  -- Stimuli
+  --   MM slave accesses via file IO
+  tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2;    -- Testbench MM clock
+  
+  p_mm_stimuli : PROCESS
+    CONSTANT c_mm_file_reg_stat_enable   : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE";
+    CONSTANT c_mm_file_reg_stat_hdr_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_INFO";
+    VARIABLE v_bsn                       : NATURAL;
+  BEGIN
+    -- Wait for DUT power up after reset
+    WAIT FOR 1 us;
+    
+    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+    -- Enable BS
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                   0, tb_clk);
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                   1, tb_clk);  -- Init BSN = 0
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_block_per_pps, tb_clk);  -- nof_block_per_sync
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,        16#00000003#, tb_clk);  -- Enable BS at PPS
+    
+    -- Enable WG
+    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
+    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
+    --   1 : phase[15:0]
+    --   2 : freq[30:0]
+    --   3 : ampl[16:0]
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0,                                                      1024 * 2**16 + 1, tb_clk);  -- nof_samples, mode calc
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1,                                 INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);  -- freq
+    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3,                            INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);  -- ampl
+
+    -- Read current BSN
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
+    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+    proc_common_wait_some_cycles(tb_clk, 1);
+    
+    -- Write scheduler BSN to trigger start of WG at next block
+    v_bsn := TO_UINT(current_bsn_wg) + 2;
+    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+    v_bsn := c_bsn_start_wg;
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);  -- first write low then high part
+    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,     0, tb_clk);  -- assume v_bsn < 2**31-1
+    
+    -- Wait for ADUH monitor to have filled with WG data
+    WAIT FOR c_sdp_T_sub * c_sdp_N_taps;
+    WAIT FOR c_sdp_T_sub * 2;
+
+    -- Offload enable
+    mmf_mm_bus_wr(c_mm_file_reg_stat_enable, 0, 1, tb_clk);
+    
+    -- End Simulation
+    proc_common_wait_until_high(ext_clk, eth_done);
+    proc_common_wait_some_cycles(ext_clk, 100);
+    proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end);
+    WAIT;
+  END PROCESS;
+
+  -- >> Verify proper DUT output using Ethernet packet statistics <<
+  u_eth_statistics : ENTITY eth_lib.eth_statistics
+    GENERIC MAP (
+      g_runtime_nof_packets => c_eth_check_nof_packets,
+      g_runtime_timeout     => c_eth_runtime_timeout,
+      g_check_nof_valid     => TRUE,
+      g_check_nof_valid_ref => c_eth_check_nof_packets
+    )
+  PORT MAP (  
+    eth_serial_in => eth_txp(0),
+    tb_end        => eth_done
+  );
+
+END tb;

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd

@@ -51,7 +51,7 @@ ENTITY node_sdp_filterbank IS
     g_sim                    : BOOLEAN := FALSE;
     g_wpfb                   : t_wpfb := c_sdp_wpfb_subbands;
     g_scope_selected_subband : NATURAL := 0;
-    g_offload_time           : NATURAL := 0    
+    g_offload_time           : NATURAL := c_sdp_offload_time
   );
   PORT (
     dp_clk        : IN  STD_LOGIC;

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -110,6 +110,9 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_marker_bst : NATURAL := 66;  -- = 0x42 = 'B'
   CONSTANT c_sdp_marker_xst : NATURAL := 88;  -- = 0x58 = 'X'
 
+  CONSTANT c_sdp_offload_time : NATURAL := 13000;  -- from wave window 62855nS / 5nS = 12571 cycles.
+ 
+
   -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1, 
   -- therefore these parameters are not explicitly used in calculation of derived constants
   -- LTS 2020_11_23:

applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd

@@ -44,7 +44,7 @@ USE work.sdp_pkg.ALL;
 ENTITY sdp_statistics_offload IS
   GENERIC (
     g_statistics_type : STRING  := "SST";
-    g_offload_time    : NATURAL := 13000;  -- from wave window 62855nS / 5nS = 12571 cycles.
+    g_offload_time    : NATURAL := c_sdp_offload_time;
     g_beamset_id      : NATURAL := 0
   );
   PORT (