Added regression_test_vhdl key, but no self checking tb available (yet).

libraries/io/epcs/hdllib.cfg

@@ -11,6 +11,9 @@ synth_files =
 test_bench_files = 
     tb/vhdl/tb_mms_epcs.vhd
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/io/fpga_sense/hdllib.cfg

@@ -9,6 +9,9 @@ synth_files =
 
 test_bench_files = 
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/io/mac_10g/hdllib.cfg

@@ -9,6 +9,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/io/remu/hdllib.cfg

@@ -10,6 +10,9 @@ synth_files =
 
 test_bench_files = 
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]