Add unb2c_test_1GbE_II revision.

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg

+hdl_lib_name = unb2c_test_1GbE_II
+hdl_library_clause_name = unb2c_test_1GbE_II_lib
+hdl_lib_uses_synth = common mm technology unb2c_board unb2c_test
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_arria10_e2sg
+hdl_lib_include_ip = 
+
+synth_files =
+    unb2c_test_1GbE_II.vhd
+
+test_bench_files = 
+    tb_unb2c_test_1GbE_II.vhd
+
+regression_test_vhdl =
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+    quartus .
+    ../../quartus .
+
+quartus_qsf_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+quartus_sdc_pre_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+
+quartus_sdc_files =
+    $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+    quartus/unb2c_test_1GbE_II_pins.tcl
+
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
+
+quartus_ip_files =
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bg_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_hdr_dat.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_tx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_tx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_bsn_monitor_v2_rx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_I_strobe_total_count_rx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bg_ctrl.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_hdr_dat.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_tx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_bsn_monitor_v2_rx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_tx.ip
+    $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth1g_II_strobe_total_count_rx.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: E. Kooistra
+-- Purpose: Tb to try loading design in simulator
+-- Description:
+-- Usage:
+-- > run 1 us.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_unb2c_test_1GbE_II IS
+END tb_unb2c_test_1GbE_II;
+
+
+ARCHITECTURE tb OF tb_unb2c_test_1GbE_II IS
+
+  SIGNAL clk  : STD_LOGIC := '0';
+  SIGNAL pps  : STD_LOGIC := '0';
+  SIGNAL wdi  : STD_LOGIC := '0';
+
+  SIGNAL eth_clk   : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  SIGNAL eth_sgin  : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL eth_sgout : STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+BEGIN
+
+  clk <= NOT clk AFTER 5 ns;
+  eth_clk(0) <= NOT eth_clk(0) AFTER 8 ns;
+  eth_clk(1) <= NOT eth_clk(1) AFTER 8 ns;
+
+  eth_sgin <= eth_sgout;  -- loopback eth0 and eth1
+
+  u_unb2c_test_1GbE_II : ENTITY work.unb2c_test_1GbE_II
+  GENERIC MAP (
+    g_sim        => TRUE
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => clk,
+    PPS          => pps,
+    WDI          => wdi,
+    INTA         => OPEN,
+    INTB         => OPEN,
+
+    -- Others
+    VERSION      => "00",
+    ID           => "00000000",
+    TESTIO       => OPEN,
+
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_sgin,
+    ETH_SGOUT    => eth_sgout,
+
+    QSFP_LED     => OPEN
+  );
+
+END tb;
+

boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Eric Kooistra
+-- Purpose: Test both 1GbE-I and 1GbE-II ports using eth_tester
+-- Description:
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, unb2c_test_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2c_test_1GbE_II IS
+  GENERIC (
+    g_design_name      : STRING  := "unb2c_test_1GbE_II";
+    g_design_note      : STRING  := "Use Eth0 and Eth1";
+    g_sim              : BOOLEAN := FALSE; --Overridden by TB
+    g_sim_unb_nr       : NATURAL := 0;
+    g_sim_node_nr      : NATURAL := 0;
+    g_stamp_date       : NATURAL := 0;  -- Date (YYYYMMDD) -- set by QSF
+    g_stamp_time       : NATURAL := 0;  -- Time (HHMMSS)   -- set by QSF
+    g_revision_id      : STRING  := ""  -- revision ID     -- set by QSF
+  );
+  PORT (
+    -- GENERAL
+    CLK          : IN    STD_LOGIC; -- System Clock
+    PPS          : IN    STD_LOGIC; -- System Sync
+    WDI          : OUT   STD_LOGIC; -- Watchdog Clear
+    INTA         : INOUT STD_LOGIC; -- FPGA interconnect line
+    INTB         : INOUT STD_LOGIC; -- FPGA interconnect line
+
+    -- Others
+    VERSION      : IN    STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+    ID           : IN    STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+    TESTIO       : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+    
+  
+    -- 1GbE Control Interface
+    ETH_CLK      : IN    STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+    ETH_SGIN     : IN    STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+    ETH_SGOUT    : OUT   STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+    QSFP_LED     : OUT   STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+  );
+END unb2c_test_1GbE_II;
+
+
+ARCHITECTURE str OF unb2c_test_1GbE_II IS
+
+BEGIN
+  u_revision : ENTITY unb2c_test_lib.unb2c_test
+  GENERIC MAP (
+    g_design_name => g_design_name,
+    g_design_note => g_design_note,
+    g_sim         => g_sim,
+    g_sim_unb_nr  => g_sim_unb_nr,
+    g_sim_node_nr => g_sim_node_nr,
+    g_stamp_date  => g_stamp_date,
+    g_stamp_time  => g_stamp_time,
+    g_revision_id => g_revision_id
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => CLK,
+    PPS          => PPS,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => VERSION,
+    ID           => ID,
+    TESTIO       => TESTIO,
+
+
+    -- 1GbE Control Interface
+    ETH_clk      => ETH_clk,
+    ETH_SGIN     => ETH_SGIN,
+    ETH_SGOUT    => ETH_SGOUT,
+
+    QSFP_LED     => QSFP_LED
+  );
+END str;