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Commit 37a278a9 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-756' into 'master' 

Resolve L2SDP-756

Closes L2SDP-756

See merge request desp/hdl!260
parents 8e949cbe 980f483f
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1 merge request!260Resolve L2SDP-756
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Stage: simulation
Stage: synthesis
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applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs_common_mm_0.ip 0 → 100644
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<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_ddrctrl_avs_common_mm_0</ipxact:library>
<ipxact:name>avs_common_mm_0</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
<ipxact:name>system</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>clk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>csi_system_clk</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="clockRate" type="longint">
<ipxact:name>clockRate</ipxact:name>
<ipxact:displayName>Clock rate</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="externallyDriven" type="bit">
<ipxact:name>externallyDriven</ipxact:name>
<ipxact:displayName>Externally driven</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="ptfSchematicName" type="string">
<ipxact:name>ptfSchematicName</ipxact:name>
<ipxact:displayName>PTF schematic name</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>system_reset</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>reset</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>csi_system_reset</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>Associated clock</ipxact:displayName>
<ipxact:value>system</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="synchronousEdges" type="string">
<ipxact:name>synchronousEdges</ipxact:name>
<ipxact:displayName>Synchronous edges</ipxact:displayName>
<ipxact:value>DEASSERT</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>mem</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>address</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>avs_mem_address</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>write</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>avs_mem_write</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>writedata</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>avs_mem_writedata</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>read</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>avs_mem_read</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>readdata</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>avs_mem_readdata</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="addressAlignment" type="string">
<ipxact:name>addressAlignment</ipxact:name>
<ipxact:displayName>Slave addressing</ipxact:displayName>
<ipxact:value>DYNAMIC</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressGroup" type="int">
<ipxact:name>addressGroup</ipxact:name>
<ipxact:displayName>Address group</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressSpan" type="string">
<ipxact:name>addressSpan</ipxact:name>
<ipxact:displayName>Address span</ipxact:displayName>
<ipxact:value>8</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="addressUnits" type="string">
<ipxact:name>addressUnits</ipxact:name>
<ipxact:displayName>Address units</ipxact:displayName>
<ipxact:value>WORDS</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
<ipxact:name>alwaysBurstMaxBurst</ipxact:name>
<ipxact:displayName>Always burst maximum burst</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>Associated clock</ipxact:displayName>
<ipxact:value>system</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>Associated reset</ipxact:displayName>
<ipxact:value>system_reset</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bitsPerSymbol" type="int">
<ipxact:name>bitsPerSymbol</ipxact:name>
<ipxact:displayName>Bits per symbol</ipxact:displayName>
<ipxact:value>8</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bridgedAddressOffset" type="string">
<ipxact:name>bridgedAddressOffset</ipxact:name>
<ipxact:displayName>Bridged Address Offset</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bridgesToMaster" type="string">
<ipxact:name>bridgesToMaster</ipxact:name>
<ipxact:displayName>Bridges to master</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
<ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
<ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="burstcountUnits" type="string">
<ipxact:name>burstcountUnits</ipxact:name>
<ipxact:displayName>Burstcount units</ipxact:displayName>
<ipxact:value>WORDS</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="constantBurstBehavior" type="bit">
<ipxact:name>constantBurstBehavior</ipxact:name>
<ipxact:displayName>Constant burst behavior</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="explicitAddressSpan" type="string">
<ipxact:name>explicitAddressSpan</ipxact:name>
<ipxact:displayName>Explicit address span</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="holdTime" type="int">
<ipxact:name>holdTime</ipxact:name>
<ipxact:displayName>Hold</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="interleaveBursts" type="bit">
<ipxact:name>interleaveBursts</ipxact:name>
<ipxact:displayName>Interleave bursts</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="isBigEndian" type="bit">
<ipxact:name>isBigEndian</ipxact:name>
<ipxact:displayName>Big endian</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="isFlash" type="bit">
<ipxact:name>isFlash</ipxact:name>
<ipxact:displayName>Flash memory</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="isMemoryDevice" type="bit">
<ipxact:name>isMemoryDevice</ipxact:name>
<ipxact:displayName>Memory device</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
<ipxact:name>isNonVolatileStorage</ipxact:name>
<ipxact:displayName>Non-volatile storage</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="linewrapBursts" type="bit">
<ipxact:name>linewrapBursts</ipxact:name>
<ipxact:displayName>Linewrap bursts</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
<ipxact:name>maximumPendingReadTransactions</ipxact:name>
<ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
<ipxact:name>maximumPendingWriteTransactions</ipxact:name>
<ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="minimumReadLatency" type="int">
<ipxact:name>minimumReadLatency</ipxact:name>
<ipxact:displayName>minimumReadLatency</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="minimumResponseLatency" type="int">
<ipxact:name>minimumResponseLatency</ipxact:name>
<ipxact:displayName>Minimum response latency</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
<ipxact:name>minimumUninterruptedRunLength</ipxact:name>
<ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="printableDevice" type="bit">
<ipxact:name>printableDevice</ipxact:name>
<ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
<ipxact:displayName>Read wait states</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitTime" type="int">
<ipxact:name>readWaitTime</ipxact:name>
<ipxact:displayName>Read wait</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="registerIncomingSignals" type="bit">
<ipxact:name>registerIncomingSignals</ipxact:name>
<ipxact:displayName>Register incoming signals</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
<ipxact:name>registerOutgoingSignals</ipxact:name>
<ipxact:displayName>Register outgoing signals</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="setupTime" type="int">
<ipxact:name>setupTime</ipxact:name>
<ipxact:displayName>Setup</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="timingUnits" type="string">
<ipxact:name>timingUnits</ipxact:name>
<ipxact:displayName>Timing units</ipxact:displayName>
<ipxact:value>Cycles</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="transparentBridge" type="bit">
<ipxact:name>transparentBridge</ipxact:name>
<ipxact:displayName>Transparent bridge</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="waitrequestAllowance" type="int">
<ipxact:name>waitrequestAllowance</ipxact:name>
<ipxact:displayName>Waitrequest allowance</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
<ipxact:name>wellBehavedWaitrequest</ipxact:name>
<ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="writeLatency" type="int">
<ipxact:name>writeLatency</ipxact:name>
<ipxact:displayName>Write latency</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="writeWaitStates" type="int">
<ipxact:name>writeWaitStates</ipxact:name>
<ipxact:displayName>Write wait states</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="writeWaitTime" type="int">
<ipxact:name>writeWaitTime</ipxact:name>
<ipxact:displayName>Write wait</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
<ipxact:vendorExtensions>
<altera:altera_assignments>
<ipxact:parameters>
<ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
<ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
<ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
<ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
<ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_assignments>
</ipxact:vendorExtensions>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>reset</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_reset_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>clk</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_clk_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>address</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_address_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>write</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_write_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>writedata</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_writedata_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>read</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_read_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>readdata</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>export</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>coe_readdata_export</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</ipxact:busInterface>
</ipxact:busInterfaces>
<ipxact:model>
<ipxact:views>
<ipxact:view>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
</ipxact:view>
</ipxact:views>
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:moduleName>avs_common_mm</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
<ipxact:ports>
<ipxact:port>
<ipxact:name>csi_system_clk</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>csi_system_reset</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>avs_mem_address</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>avs_mem_write</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>avs_mem_writedata</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>31</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>avs_mem_read</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>avs_mem_readdata</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>31</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_reset_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_clk_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_address_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_write_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_writedata_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>31</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_read_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>coe_readdata_export</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:vectors>
<ipxact:vector>
<ipxact:left>0</ipxact:left>
<ipxact:right>31</ipxact:right>
</ipxact:vector>
</ipxact:vectors>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
</ipxact:ports>
</ipxact:model>
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_ddrctrl_avs_common_mm_0</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="g_adr_w" type="int">
<ipxact:name>g_adr_w</ipxact:name>
<ipxact:displayName>g_adr_w</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="g_dat_w" type="int">
<ipxact:name>g_dat_w</ipxact:name>
<ipxact:displayName>g_dat_w</ipxact:displayName>
<ipxact:value>32</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
<ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
<ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
<ipxact:value>-1</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="device" type="string">
<ipxact:name>device</ipxact:name>
<ipxact:displayName>Device</ipxact:displayName>
<ipxact:value>10AX115U3F45E2SG</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceFamily" type="string">
<ipxact:name>deviceFamily</ipxact:name>
<ipxact:displayName>Device family</ipxact:displayName>
<ipxact:value>Arria 10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
<ipxact:displayName>Generation Id</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bonusData" type="string">
<ipxact:name>bonusData</ipxact:name>
<ipxact:displayName>bonusData</ipxact:displayName>
<ipxact:value>bonusData
{
}
</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
<ipxact:name>hideFromIPCatalog</ipxact:name>
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
<ipxact:value>&lt;boundaryDefinition&gt;
&lt;interfaces&gt;
&lt;interface&gt;
&lt;name&gt;system&lt;/name&gt;
&lt;type&gt;clock&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;csi_system_clk&lt;/name&gt;
&lt;role&gt;clk&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;clockRate&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;externallyDriven&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ptfSchematicName&lt;/key&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;system_reset&lt;/name&gt;
&lt;type&gt;reset&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;csi_system_reset&lt;/name&gt;
&lt;role&gt;reset&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;value&gt;system&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;synchronousEdges&lt;/key&gt;
&lt;value&gt;DEASSERT&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;mem&lt;/name&gt;
&lt;type&gt;avalon&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;avs_mem_address&lt;/name&gt;
&lt;role&gt;address&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;port&gt;
&lt;name&gt;avs_mem_write&lt;/name&gt;
&lt;role&gt;write&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;port&gt;
&lt;name&gt;avs_mem_writedata&lt;/name&gt;
&lt;role&gt;writedata&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;32&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;port&gt;
&lt;name&gt;avs_mem_read&lt;/name&gt;
&lt;role&gt;read&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;port&gt;
&lt;name&gt;avs_mem_readdata&lt;/name&gt;
&lt;role&gt;readdata&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;32&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap&gt;
&lt;entry&gt;
&lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;/assignmentValueMap&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;addressAlignment&lt;/key&gt;
&lt;value&gt;DYNAMIC&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;addressGroup&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;addressSpan&lt;/key&gt;
&lt;value&gt;8&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;addressUnits&lt;/key&gt;
&lt;value&gt;WORDS&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;value&gt;system&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;value&gt;system_reset&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;bitsPerSymbol&lt;/key&gt;
&lt;value&gt;8&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;bridgedAddressOffset&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;bridgesToMaster&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;burstcountUnits&lt;/key&gt;
&lt;value&gt;WORDS&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;constantBurstBehavior&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;explicitAddressSpan&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;holdTime&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;interleaveBursts&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;isBigEndian&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;isFlash&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;isMemoryDevice&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;isNonVolatileStorage&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;linewrapBursts&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;minimumReadLatency&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;minimumResponseLatency&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;printableDevice&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readLatency&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readWaitStates&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readWaitTime&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;registerIncomingSignals&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;registerOutgoingSignals&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;setupTime&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;timingUnits&lt;/key&gt;
&lt;value&gt;Cycles&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;transparentBridge&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;waitrequestAllowance&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;writeLatency&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;writeWaitStates&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;writeWaitTime&lt;/key&gt;
&lt;value&gt;0&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;reset&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_reset_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;clk&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_clk_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;address&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_address_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;write&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_write_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;writedata&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_writedata_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;32&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;read&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_read_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Output&lt;/direction&gt;
&lt;width&gt;1&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;interface&gt;
&lt;name&gt;readdata&lt;/name&gt;
&lt;type&gt;conduit&lt;/type&gt;
&lt;isStart&gt;false&lt;/isStart&gt;
&lt;ports&gt;
&lt;port&gt;
&lt;name&gt;coe_readdata_export&lt;/name&gt;
&lt;role&gt;export&lt;/role&gt;
&lt;direction&gt;Input&lt;/direction&gt;
&lt;width&gt;32&lt;/width&gt;
&lt;lowerBound&gt;0&lt;/lowerBound&gt;
&lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
&lt;/port&gt;
&lt;/ports&gt;
&lt;assignments&gt;
&lt;assignmentValueMap/&gt;
&lt;/assignments&gt;
&lt;parameters&gt;
&lt;parameterValueMap&gt;
&lt;entry&gt;
&lt;key&gt;associatedClock&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;associatedReset&lt;/key&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;prSafe&lt;/key&gt;
&lt;value&gt;false&lt;/value&gt;
&lt;/entry&gt;
&lt;/parameterValueMap&gt;
&lt;/parameters&gt;
&lt;/interface&gt;
&lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemInfos" type="string">
<ipxact:name>systemInfos</ipxact:name>
<ipxact:displayName>systemInfos</ipxact:displayName>
<ipxact:value>&lt;systemInfosDefinition&gt;
&lt;connPtSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;mem&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos/&gt;
&lt;consumedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;ADDRESS_MAP&lt;/key&gt;
&lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
&lt;value&gt;3&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
&lt;value&gt;32&lt;/value&gt;
&lt;/entry&gt;
&lt;/consumedSystemInfos&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;system&lt;/key&gt;
&lt;value&gt;
&lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
&lt;suppliedSystemInfos&gt;
&lt;entry&gt;
&lt;key&gt;CLOCK_RATE&lt;/key&gt;
&lt;value&gt;-1&lt;/value&gt;
&lt;/entry&gt;
&lt;/suppliedSystemInfos&gt;
&lt;consumedSystemInfos/&gt;
&lt;/value&gt;
&lt;/entry&gt;
&lt;/connPtSystemInfos&gt;
&lt;/systemInfosDefinition&gt;</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="avs_common_mm_0.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="avs_common_mm_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="avs_common_mm_0.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="avs_common_mm_0.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="avs_common_mm_0.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="avs_common_mm_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="avs_common_mm_0.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="avs_common_mm_0.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="avs_common_mm_0.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="avs_common_mm_0.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</ipxact:vendorExtensions>
</ipxact:component>
\ No newline at end of file
applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/qsys_lofar2_unb2c_ddrctrl.qsys
+ 41
− 41
View file @ 37a278a9
......@@ -4565,47 +4565,6 @@
</componentDefinition>]]></parameter>
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>clk_out</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>clk_in</value>
</entry>
<entry>
<key>clockRate</key>
<value>125000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>clk_in</name>
<type>clock</type>
......@@ -4678,6 +4637,47 @@
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>clk</name>
<type>clock</type>
<isStart>true</isStart>
<ports>
<port>
<name>clk_out</name>
<role>clk</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
<assignmentValueMap/>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>associatedDirectClock</key>
<value>clk_in</value>
</entry>
<entry>
<key>clockRate</key>
<value>125000000</value>
</entry>
<entry>
<key>clockRateKnown</key>
<value>true</value>
</entry>
<entry>
<key>externallyDriven</key>
<value>true</value>
</entry>
<entry>
<key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
<name>clk_reset</name>
<type>reset</type>
applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+ 6
− 0
View file @ 37a278a9
......@@ -95,6 +95,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
CONSTANT c_mm_file_reg_bsn_buf : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_BUF";
CONSTANT c_mm_file_ram_bsn_buf : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BSN_BUF";
CONSTANT c_mm_file_reg_rx_seq_bsn : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_RX_SEQ_BSN";
CONSTANT c_mm_file_reg_ddrctrl_ctrl_state : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DDRCTRL_CTRL_STATE";
-- c_check_vector
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr4_sim_16k;
......@@ -137,6 +138,10 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
SIGNAL sosi_out_data_sin : STD_LOGIC_VECTOR( c_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sosi_out_not_bsn : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL out_ddrctrl_ctrl_state : STD_LOGIC_VECTOR(c_rd_data_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
......@@ -277,6 +282,7 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
WAIT FOR c_mm_clk_period*50000;
mmf_mm_bus_rd(c_mm_file_reg_ddrctrl_ctrl_state, 0, out_ddrctrl_ctrl_state, tb_clk);
FOR I IN 0 TO c_bim-1 LOOP
FOR J IN 0 TO c_nof_streams-1 LOOP
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 13
− 2
View file @ 37a278a9
......@@ -139,10 +139,17 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL bsn_co : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL data_stopped : STD_LOGIC;
SIGNAL state_vec : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL ddrctrl_ctrl_state_local : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL ctlr_wr_flush_en : STD_LOGIC;
BEGIN
rd_siso.ready <= rd_ready;
rd_siso.xon <= '1';
ddrctrl_ctrl_state(5 DOWNTO 0) <= ddrctrl_ctrl_state_local(5 DOWNTO 0);
ddrctrl_ctrl_state(7 DOWNTO 6) <= state_vec(1 DOWNTO 0);
ddrctrl_ctrl_state(32-1 DOWNTO 8) <= ddrctrl_ctrl_state_local(32-1 DOWNTO 8);
-- input to io_ddr
u_ddrctrl_input : ENTITY work.ddrctrl_input
......@@ -203,6 +210,8 @@ BEGIN
-- MM interface
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
state_vec => state_vec,
ctlr_wr_flush_en_o => ctlr_wr_flush_en,
-- Driver clock domain
dvr_clk => clk,
......@@ -302,6 +311,8 @@ BEGIN
wr_sosi => wr_sosi,
wr_fifo_usedw => wr_fifo_usedw,
rd_fifo_usedw => rd_fifo_usedw,
ctlr_wr_flush_en => ctlr_wr_flush_en,
flush_state => state_vec,
-- ddrctrl_output
outp_bsn => bsn_co,
......@@ -309,7 +320,7 @@ BEGIN
-- ddrctrl_controller
stop_in => stop_in,
stop_out => stop,
ddrctrl_ctrl_state => ddrctrl_ctrl_state
ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
);
END str;
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+ 88
− 30
View file @ 37a278a9
......@@ -70,8 +70,11 @@ ENTITY ddrctrl_controller IS
dvr_mosi : OUT t_mem_ctlr_mosi;
dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi;
wr_siso : IN t_dp_siso;
wr_fifo_usedw : IN STD_LOGIC_VECTOR(g_wr_fifo_uw_w-1 DOWNTO 0);
rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
ctlr_wr_flush_en : IN STD_LOGIC;
flush_state : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-- ddrctrl_output
outp_bsn : OUT STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
......@@ -87,19 +90,40 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
CONSTANT c_bitshift_w : NATURAL := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
CONSTANT c_adr_w : NATURAL := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
CONSTANT c_pof_ma : NATURAL := NATURAL((((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/REAL(g_adr_per_b))*REAL(g_adr_per_b)); --percentage of max address.
CONSTANT c_pof_ma : NATURAL := ((NATURAL((REAL(g_max_adr)*(100.0-REAL(g_stop_percentage)))/100.0)/g_adr_per_b)*g_adr_per_b); --percentage of max address.
CONSTANT c_zeros : STD_LOGIC_VECTOR(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT c_stop_adr_zeros : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0) := (OTHERS => '0');
-- constant for reading
CONSTANT c_rd_data_w : NATURAL := g_nof_streams*g_out_data_w; -- 168
CONSTANT c_rest : NATURAL := c_rd_data_w-(g_wr_data_w mod c_rd_data_w); -- 96
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
-- constant for debugging
CONSTANT c_always_one_ndx : NATURAL := 0;
CONSTANT c_rst_ndx : NATURAL := 1;
CONSTANT c_low_state_ndx : NATURAL := 2;
CONSTANT c_high_state_ndx : NATURAL := 5;
CONSTANT c_state_ndx_w : NATURAL := c_high_state_ndx-c_low_state_ndx+1;
CONSTANT c_low_bsn_ndx : NATURAL := 16;
CONSTANT c_high_bsn_ndx : NATURAL := 25;
CONSTANT c_bsn_ndx_w : NATURAL := c_high_bsn_ndx-c_low_bsn_ndx+1;
CONSTANT c_start_bsn : NATURAL := 14;
CONSTANT c_low_adr_ndx : NATURAL := c_high_bsn_ndx+1;
CONSTANT c_high_adr_ndx : NATURAL := 32-1;
CONSTANT c_adr_ndx_w : NATURAL := c_high_adr_ndx-c_low_adr_ndx+1;
CONSTANT c_done_ndx : NATURAL := 8;
CONSTANT c_bb_ndx : NATURAL := 9;
CONSTANT c_ben_ndx : NATURAL := 10;
CONSTANT c_das_ndx : NATURAL := 11;
CONSTANT c_low_bre_ndx : NATURAL := 12;
CONSTANT c_high_bre_ndx : NATURAL := 15;
CONSTANT c_bre_ndx_w : NATURAL := c_high_bre_ndx-c_low_bre_ndx+1;
-- type for statemachine
TYPE t_state IS (RESET, STOP_READING, WAIT_FOR_SOP, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING);
TYPE t_state IS (RESET, STOP_FLUSH, STOP_READING, WAIT_FOR_SOP, WRITING, SET_STOP, STOP_WRITING, LAST_WRITE_BURST, START_READING, READING);
-- record for readability
TYPE t_reg IS RECORD
......@@ -107,6 +131,9 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
state : t_state;
started : STD_LOGIC;
-- stopping flush
timer : NATURAL;
-- stopping signals
ready_for_set_stop : STD_LOGIC;
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
......@@ -130,7 +157,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
ddrctrl_ctrl_state : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
END RECORD;
CONSTANT c_t_reg_init : t_reg := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (OTHERS => '0'));
CONSTANT c_t_reg_init : t_reg := (RESET, '0', 4, '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (OTHERS => '0'));
-- signals for readability
......@@ -151,31 +178,51 @@ BEGIN
v := q_reg;
v.wr_sosi := inp_sosi;
--v.ddrctrl_ctrl_state(c_high_bsn_ndx DOWNTO c_low_bsn_ndx) := inp_sosi.bsn(c_start_bsn+c_bsn_ndx_w-1 DOWNTO c_start_bsn);
--v.ddrctrl_ctrl_state(c_high_adr_ndx DOWNTO c_low_adr_ndx) := TO_UVEC(inp_adr, 32)(c_adr_ndx_w-1 DOWNTO 0);
CASE q_reg.state IS
WHEN RESET =>
v := c_t_reg_init;
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(0, c_state_ndx_w);
IF rst = '0' AND wr_siso.ready = '1' THEN
v.state := STOP_FLUSH;
v.timer := 0;
END IF;
WHEN STOP_FLUSH =>
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
v.wr_sosi.valid := '0';
IF flush_state = "10" THEN
v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
v.dvr_mosi.wr := '1';
ELSIF flush_state = "11" AND q_reg.timer = 0 THEN
v.wr_sosi.valid := '1';
v.ddrctrl_ctrl_state(32-1) := rst;
v.timer := 127;
END IF;
IF rst = '0' THEN
v.state := STOP_READING;
IF q_reg.timer > 0 AND rst = '0' THEN
v.timer := q_reg.timer-1;
END IF;
IF flush_state = "01" THEN
v.state := WAIT_FOR_SOP;
v.stopped := '0';
END IF;
WHEN STOP_READING =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(1, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
-- this is the last read burst, this make sure every data containing word in the memory has been read.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
v.dvr_mosi.burstbegin := '1';
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0);
v.dvr_mosi.burstsize := TO_UVEC(q_reg.stop_burstsize, dvr_mosi.burstsize'length);
v.stopped := '0';
v.wr_sosi.valid := '0';
v.wr_sosi.valid := '1';
v.state := WAIT_FOR_SOP;
v.wr_burst_en := '1';
v.rst_ddrctrl_input_ac := '1';
......@@ -191,11 +238,14 @@ BEGIN
WHEN WAIT_FOR_SOP =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(2, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
v.dvr_mosi.burstbegin := '0';
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := (OTHERS => '0');
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
v.rst_ddrctrl_input_ac := '0';
IF q_reg.started = '0' AND inp_sosi.eop = '1' THEN
v.wr_sosi.valid := '1';
v.wr_sosi.valid := '0';
ELSIF inp_sosi.sop = '1' THEN
v.state := WRITING;
ELSE
......@@ -204,7 +254,7 @@ BEGIN
WHEN WRITING =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(3, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
-- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF q_reg.wr_bursts_ready >= 1 AND dvr_miso.done = '1' AND q_reg.wr_burst_en = '1' AND q_reg.dvr_mosi.burstbegin = '0' THEN
......@@ -242,7 +292,7 @@ BEGIN
WHEN SET_STOP =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(4, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
-- this state sets a stop address dependend on the g_stop_percentage.
IF inp_adr-c_pof_ma >= 0 THEN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w);
......@@ -250,13 +300,13 @@ BEGIN
v.stop_adr(c_adr_w-1 DOWNTO 0) := TO_UVEC(inp_adr+g_max_adr-c_pof_ma, c_adr_w);
END IF;
v.ready_for_set_stop := '0';
IF TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0)) = 0 THEN
IF v.stop_adr(c_adr_w-1 DOWNTO 0) = c_stop_adr_zeros(c_adr_w-1 DOWNTO 0) THEN
v.last_adr_to_write_to(c_adr_w-1 DOWNTO 0) := TO_UVEC(g_max_adr-g_last_burstsize, c_adr_w);
ELSE
v.last_adr_to_write_to(c_adr_w-1 DOWNTO c_bitshift_w) := v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_w);
END IF;
v.last_adr_to_write_to(c_bitshift_w-1 DOWNTO 0) := (OTHERS => '0');
v.stop_burstsize := TO_UINT(v.stop_adr(c_adr_w-1 DOWNTO 0))-TO_UINT(v.last_adr_to_write_to)+1;
v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w-1 DOWNTO 0),-1*TO_UINT(v.last_adr_to_write_to)),1));
-- still a write cyle
-- if adr mod g_burstsize = 0
......@@ -292,7 +342,7 @@ BEGIN
WHEN STOP_WRITING =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(5, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
-- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
v.wr_sosi.valid := '0';
v.dvr_mosi.burstbegin := '0';
......@@ -300,7 +350,7 @@ BEGIN
v.stop_adr := TO_UVEC(g_max_adr, c_adr_w);
-- still receiving write data.
v.wr_bursts_ready := TO_UINT(TO_UVEC(TO_UINT(wr_fifo_usedw)+2, g_wr_fifo_uw_w)(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
v.wr_bursts_ready := TO_UINT(INCR_UVEC(wr_fifo_usedw, 2)(g_wr_fifo_uw_w-1 DOWNTO c_bitshift_w));
IF NOT (q_reg.wr_bursts_ready = 0) AND q_reg.dvr_mosi.burstbegin = '0'THEN
v.wr_burst_en := '1';
ELSIF q_reg.wr_bursts_ready = 0 THEN
......@@ -329,7 +379,7 @@ BEGIN
WHEN LAST_WRITE_BURST =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(6, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
v.wr_sosi.valid := '0';
IF dvr_miso.done = '1' THEN
......@@ -351,7 +401,7 @@ BEGIN
WHEN START_READING =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(7, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0';
v.outp_bsn := INCR_UVEC(inp_sosi.bsn,-1*g_bim);
......@@ -364,7 +414,7 @@ BEGIN
v.read_adr := g_burstsize;
ELSE
v.dvr_mosi.burstsize(dvr_mosi.burstsize'length-1 DOWNTO 0) := TO_UVEC(g_burstsize-q_reg.stop_burstsize, dvr_mosi.burstsize'length);
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := TO_UVEC(TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+q_reg.stop_burstsize, c_adr_w);
v.dvr_mosi.address(c_adr_w-1 DOWNTO 0) := INCR_UVEC(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0), q_reg.stop_burstsize);
v.read_adr := TO_UINT(q_reg.last_adr_to_write_to(c_adr_w-1 DOWNTO 0))+g_burstsize;
END IF;
v.dvr_mosi.burstbegin := '1';
......@@ -381,7 +431,7 @@ BEGIN
WHEN READING =>
v.ddrctrl_ctrl_state(32-1 DOWNTO 0) := TO_UVEC(8, 32);
v.ddrctrl_ctrl_state(c_high_state_ndx DOWNTO c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
v.wr_sosi.valid := '0';
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
IF TO_UINT(rd_fifo_usedw) <= g_burstsize AND dvr_miso.done = '1' AND q_reg.rd_burst_en = '1' THEN
......@@ -424,6 +474,14 @@ BEGIN
v.started := '1';
END IF;
v.ddrctrl_ctrl_state(c_always_one_ndx) := '1';
v.ddrctrl_ctrl_state(c_rst_ndx) := rst;
v.ddrctrl_ctrl_state(c_done_ndx) := dvr_miso.done;
v.ddrctrl_ctrl_state(c_bb_ndx) := q_reg.dvr_mosi.burstbegin;
v.ddrctrl_ctrl_state(c_ben_ndx) := q_reg.wr_burst_en;
v.ddrctrl_ctrl_state(c_das_ndx) := inp_data_stopped;
v.ddrctrl_ctrl_state(c_high_bre_ndx DOWNTO c_low_bre_ndx) := TO_UVEC(q_reg.wr_bursts_ready, 32)(c_bre_ndx_w-1 DOWNTO 0);
d_reg <= v;
END PROCESS;
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+ 1
− 1
View file @ 37a278a9
......@@ -219,7 +219,7 @@ BEGIN
IF rst = '1' THEN
v.state := RESET;
ELSIF q_reg.state = RESET OR (q_reg.valid_data = '0' AND q_reg.state = OFF) OR (((g_bim+TO_UINT(in_bsn)-1) = TO_UINT(q_reg.out_sosi.bsn)) AND v.out_sosi.eop = '1') THEN
ELSIF q_reg.state = RESET OR (q_reg.valid_data = '0' AND q_reg.state = OFF) OR ((INCR_UVEC(INCR_UVEC(in_bsn, g_bim), -1)(q_reg.out_sosi.bsn'length-1 DOWNTO 0) = q_reg.out_sosi.bsn(q_reg.out_sosi.bsn'length-1 DOWNTO 0)) AND v.out_sosi.eop = '1') THEN
v.state := OFF;
ELSIF q_reg.state = OFF THEN
v.state_off := '0';
......
libraries/base/common/src/vhdl/common_fifo_dc.vhd
+ 3
− 0
View file @ 37a278a9
......@@ -39,6 +39,7 @@ ENTITY common_fifo_dc IS
wr_clk : IN STD_LOGIC;
wr_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
wr_req : IN STD_LOGIC;
wr_init_out : OUT STD_LOGIC;
wr_ful : OUT STD_LOGIC;
wrusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
rd_clk : IN STD_LOGIC;
......@@ -98,6 +99,8 @@ BEGIN
out_rst => wr_init -- assume init has finished g_delay_len cycles after release of wr_rst
);
wr_init_out <= wr_init;
-- The FIFO under read and over write protection are kept enabled in the MegaWizard
wr_en <= wr_req AND NOT wr_init; -- check on NOT ful is not necessary when overflow_checking="ON" (Altera) or according to fifo_generator_ug175.pdf (Xilinx)
rd_en <= rd_req; -- check on NOT emp is not necessary when underflow_checking="ON" (Altera)
......
libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+ 3
− 1
View file @ 37a278a9
......@@ -111,6 +111,7 @@ ARCHITECTURE str OF dp_fifo_core IS
SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0);
SIGNAL fifo_wr_req : STD_LOGIC;
SIGNAL fifo_wr_ful : STD_LOGIC;
SIGNAL wr_init : STD_LOGIC := '0';
SIGNAL fifo_wr_usedw : STD_LOGIC_VECTOR(wr_usedw'RANGE);
SIGNAL fifo_rd_dat : STD_LOGIC_VECTOR(c_fifo_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
......@@ -166,7 +167,7 @@ BEGIN
nxt_snk_out.xon <= src_in.xon;
-- up stream use fifo almost full to control snk_out.ready
nxt_snk_out.ready <= '1' WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
nxt_snk_out.ready <= NOT wr_init WHEN UNSIGNED(fifo_wr_usedw)<c_fifo_almost_full ELSE '0';
gen_common_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
u_common_fifo_sc : ENTITY common_lib.common_fifo_sc
......@@ -205,6 +206,7 @@ BEGIN
wr_clk => wr_clk,
wr_dat => fifo_wr_dat,
wr_req => fifo_wr_req,
wr_init_out => wr_init,
wr_ful => fifo_wr_ful,
wrusedw => fifo_wr_usedw,
rd_clk => rd_clk,
......
libraries/io/ddr/src/vhdl/io_ddr.vhd
+ 7
− 2
View file @ 37a278a9
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