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applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd

@@ -258,7 +258,7 @@ BEGIN
     -- Streaming clock domain
     bs_sosi           => bs_sosi,
 
-    bs_restart        => st_rst
+    bs_restart        => open 
   );
 
   u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler

applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd

@@ -80,7 +80,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_ddrctrl IS
   CONSTANT c_cable_delay     : TIME := 12 ns;
   CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoardi
   CONSTANT c_st_clk_period   : TIME := 5 ns;  -- 200 MHz st clk
-  CONSTANT c_tb_clk_period   : TIME := 1 ns;  -- 1000 MHz mm clk
+  CONSTANT c_tb_clk_period   : TIME := 1 ns;  -- 1000 MHz tb clk
+  CONSTANT c_mm_clk_period   : TIME := 10 ns; -- 100 MHz mm clk
   CONSTANT c_pps_period      : NATURAL := 1000; 
 
   CONSTANT c_mm_file_reg_bsn_source_v2        : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -239,7 +240,7 @@ BEGIN
       mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+2, INTEGER(c_wg_freq), tb_clk);  -- freq
       mmf_mm_bus_wr(c_mm_file_reg_diag_wg_wideband_arr, (I*4)+3, INTEGER(c_wg_ampl), tb_clk);  -- ampl
     END LOOP;
-
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0,     0, tb_clk);
     -- Read current BSN
     mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
     mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
@@ -252,7 +253,13 @@ BEGIN
     mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,              0, tb_clk);  -- assume v_bsn < 2**31-1
 
 
-    WAIT FOR c_st_clk_period*100000;
+    WAIT FOR c_mm_clk_period*100000;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 1**32, tb_clk);
+    WAIT FOR c_mm_clk_period*16;
+    mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0,     0, tb_clk);
+    WAIT FOR c_mm_clk_period*50000;
+
+
     tb_end <= '1';
     ASSERT FALSE  REPORT "Test: OK" SEVERITY FAILURE;
     WAIT;

applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd

@@ -128,8 +128,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
   wr_sosi                     : t_dp_sosi;
   END RECORD;
 
-
-  CONSTANT c_t_reg_init       : t_reg         := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '0', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
+  CONSTANT c_t_reg_init       : t_reg         := (RESET, '0', '0', TO_UVEC(g_max_adr, c_adr_w), (OTHERS => '0'), 0, '1', '1', '0', 0, (OTHERS => '0'), 0, '0', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
 
 
   -- signals for readability
@@ -160,11 +159,6 @@ BEGIN
       v.dvr_mosi.wr                                               := '1';
       v.wr_sosi.valid                                             := '1';
 
-      IF rst = '0' THEN
-        v.state := WAIT_FOR_SOP;
-      END IF;
-
-
 
     WHEN WAIT_FOR_SOP =>
     v.dvr_mosi.burstbegin := '0';
@@ -431,6 +425,14 @@ BEGIN
       END IF;
       -- the statemachine goes to Idle when its finished or when its waiting on other components.
 
+    WHEN OTHERS =>
+      v := c_t_reg_init;
+
+
+    END CASE;
+
+
+    IF q_reg.state = RESET OR q_reg.state = IDLE THEN
       IF stop_in = '1' THEN
         v.ready_for_set_stop := '1';
       ELSIF q_reg.ready_for_set_stop = '1' AND inp_sosi.eop = '1' THEN
@@ -444,15 +446,7 @@ BEGIN
       ELSE
         v.state := IDLE;
       END IF;
-
-
-
-    WHEN OTHERS =>
-      v := c_t_reg_init;
-
-
-    END CASE;
-
+    END IF;
 
 
     IF rst = '1' THEN