Corrected c_dsp_dat_w selection to check both input a and b.

libraries/technology/mult/tech_complex_mult.vhd

@@ -99,7 +99,7 @@ END tech_complex_mult;
 
 ARCHITECTURE str of tech_complex_mult is 
 
-  CONSTANT c_dsp_dat_w   : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w);  -- g_in_a_w = g_in_b_w
+  CONSTANT c_dsp_dat_w   : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w AND g_in_b_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w);  -- g_in_a_w = g_in_b_w
   CONSTANT c_dsp_prod_w  : NATURAL  := 2*c_dsp_dat_w;
   
   SIGNAL ar        : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);