-Renamed dp_counter to dp_counter_func as contains functional logic only

 (no pipelining).

libraries/base/dp/hdllib.cfg

@@ -129,7 +129,7 @@ synth_files =
     src/vhdl/dp_folder.vhd
     src/vhdl/dp_unfolder.vhd
     src/vhdl/dp_switch.vhd
-    src/vhdl/dp_counter.vhd
+    src/vhdl/dp_counter_func.vhd
     tb/vhdl/dp_stream_player.vhd
     tb/vhdl/dp_sosi_recorder.vhd
     tb/vhdl/dp_stream_rec_play.vhd
@@ -197,7 +197,7 @@ test_bench_files =
     tb/vhdl/tb_dp_sync_insert.vhd
     tb/vhdl/tb_dp_folder.vhd
     tb/vhdl/tb_dp_switch.vhd
-    tb/vhdl/tb_dp_counter.vhd
+    tb/vhdl/tb_dp_counter_func.vhd
 
     tb/vhdl/tb_tb_dp_block_gen.vhd
     tb/vhdl/tb_tb_dp_block_gen_arr.vhd

libraries/base/dp/src/vhdl/dp_counter.vhd → libraries/base/dp/src/vhdl/dp_counter_func.vhd

@@ -46,7 +46,7 @@ USE IEEE.numeric_std.ALL;
 USE common_lib.common_pkg.ALL;
 USE work.dp_stream_pkg.ALL;
 
-ENTITY dp_counter IS
+ENTITY dp_counter_func IS
   GENERIC (
     g_c0_trigger : BOOLEAN := FALSE; --FALSE: start counters on first valid; else use c0_trigger input pulse
     g_c0         : t_natural_arr(0 TO 2) := (0,2,1); -- (start,stop,step) like python range(start, stop, step)
@@ -72,10 +72,10 @@ ENTITY dp_counter IS
     c1_min      : OUT STD_LOGIC; --Pulses when c1=start
     c1_max      : OUT STD_LOGIC  --Pulses when c1=max AND c0=max
   );
-END dp_counter;
+END dp_counter_func;
 
 
-ARCHITECTURE rtl OF dp_counter IS
+ARCHITECTURE rtl OF dp_counter_func IS
 
   -- Start, stop, step indices in g_c0 .. g_c4
   CONSTANT c_start : NATURAL := 0;

libraries/base/dp/tb/vhdl/tb_dp_counter.vhd → libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd

@@ -23,7 +23,7 @@
 -- Author:
 -- . Daniel van der Schuur
 -- Purpose:
--- . Test bench for dp_counter
+-- . Test bench for dp_counter_func
 -- Description:
 -- . 
 --Usage:
@@ -39,17 +39,17 @@ USE common_lib.tb_common_pkg.ALL;
 USE work.dp_stream_pkg.ALL;
 USE work.tb_dp_pkg.ALL;
 
-ENTITY tb_dp_counter IS
+ENTITY tb_dp_counter_func IS
   GENERIC (
     g_c0         : t_natural_arr(0 TO 2) := (0,2,1);  -- (start,stop,step) like python range(start, stop, step)
     g_c1         : t_natural_arr(0 TO 2) := (0,2,1);
     g_flow_control_stimuli   : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
     g_flow_control_verify    : t_dp_flow_control_enum := e_active  -- always active, random or pulse flow control
   );
-END tb_dp_counter;
+END tb_dp_counter_func;
 
 
-ARCHITECTURE tb OF tb_dp_counter IS
+ARCHITECTURE tb OF tb_dp_counter_func IS
 
   ------------------------------------------------------------------------------
   -- Clock & reset
@@ -90,20 +90,20 @@ ARCHITECTURE tb OF tb_dp_counter IS
   SIGNAL stimuli_src_in   : t_dp_siso;
 
   ------------------------------------------------------------------------------
-  -- dp_counter
+  -- dp_counter_func
   ------------------------------------------------------------------------------ 
-  SIGNAL dp_counter_snk_in  : t_dp_sosi;
-  SIGNAL dp_counter_snk_out : t_dp_siso;
-  SIGNAL dp_counter_src_out : t_dp_sosi;
-  SIGNAL dp_counter_src_in  : t_dp_siso;
+  SIGNAL dp_counter_func_snk_in  : t_dp_sosi;
+  SIGNAL dp_counter_func_snk_out : t_dp_siso;
+  SIGNAL dp_counter_func_src_out : t_dp_sosi;
+  SIGNAL dp_counter_func_src_in  : t_dp_siso;
 
-  SIGNAL dp_counter_c0      : STD_LOGIC_VECTOR(ceil_log2(g_c0(0)+((g_c0(1)-1-g_c0(0))/g_c0(2))*g_c0(2)+1)-1 DOWNTO 0);
-  SIGNAL dp_counter_c0_min  : STD_LOGIC;
-  SIGNAL dp_counter_c0_max  : STD_LOGIC;
+  SIGNAL dp_counter_func_c0      : STD_LOGIC_VECTOR(ceil_log2(g_c0(0)+((g_c0(1)-1-g_c0(0))/g_c0(2))*g_c0(2)+1)-1 DOWNTO 0);
+  SIGNAL dp_counter_func_c0_min  : STD_LOGIC;
+  SIGNAL dp_counter_func_c0_max  : STD_LOGIC;
 
-  SIGNAL dp_counter_c1      : STD_LOGIC_VECTOR(ceil_log2(g_c1(0)+((g_c1(1)-1-g_c1(0))/g_c1(2))*g_c1(2)+1)-1 DOWNTO 0);
-  SIGNAL dp_counter_c1_min  : STD_LOGIC;
-  SIGNAL dp_counter_c1_max  : STD_LOGIC;
+  SIGNAL dp_counter_func_c1      : STD_LOGIC_VECTOR(ceil_log2(g_c1(0)+((g_c1(1)-1-g_c1(0))/g_c1(2))*g_c1(2)+1)-1 DOWNTO 0);
+  SIGNAL dp_counter_func_c1_min  : STD_LOGIC;
+  SIGNAL dp_counter_func_c1_max  : STD_LOGIC;
 
   ------------------------------------------------------------------------------
   -- Verification
@@ -174,12 +174,12 @@ BEGIN
   END PROCESS;
 
   ------------------------------------------------------------------------------
-  -- dp_counter
+  -- dp_counter_func
   ------------------------------------------------------------------------------ 
-  stimuli_src_in    <= c_dp_siso_rdy; --dp_counter_snk_out;
-  dp_counter_snk_in <= stimuli_src_out;
+  stimuli_src_in    <= c_dp_siso_rdy; --dp_counter_func_snk_out;
+  dp_counter_func_snk_in <= stimuli_src_out;
     
-  u_dp_counter : ENTITY work.dp_counter
+  u_dp_counter_func : ENTITY work.dp_counter_func
   GENERIC MAP (
     g_c0 => g_c0,
     g_c1 => g_c1
@@ -188,19 +188,19 @@ BEGIN
     rst       => rst,
     clk       => clk,
 
-    snk_in    => dp_counter_snk_in,
-    snk_out   => dp_counter_snk_out,
+    snk_in    => dp_counter_func_snk_in,
+    snk_out   => dp_counter_func_snk_out,
 
-    src_out   => dp_counter_src_out,
-    src_in    => dp_counter_src_in,
+    src_out   => dp_counter_func_src_out,
+    src_in    => dp_counter_func_src_in,
 
-    c0        => dp_counter_c0, 
-    c0_min    => dp_counter_c0_min,
-    c0_max    => dp_counter_c0_max,
+    c0        => dp_counter_func_c0, 
+    c0_min    => dp_counter_func_c0_min,
+    c0_max    => dp_counter_func_c0_max,
 
-    c1        => dp_counter_c1, 
-    c1_min    => dp_counter_c1_min,
-    c1_max    => dp_counter_c1_max
+    c1        => dp_counter_func_c1, 
+    c1_min    => dp_counter_func_c1_min,
+    c1_max    => dp_counter_func_c1_max
   );
   
   ------------------------------------------------------------------------------