added (older) ss and ddr3 libraries to radiohdl

libraries/base/ss/hdllib.cfg

+hdl_lib_name = ss
+hdl_library_clause_name = ss_lib
+hdl_lib_uses_synth = diag dp mm common
+hdl_lib_uses_sim = 
+
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = 
+
+synth_files =
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss_store.vhd
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss_retrieve.vhd
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss.vhd
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss_wide.vhd
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss_reorder.vhd
+    $UNB/Firmware/modules/Lofar/ss/src/vhdl/ss_parallel.vhd
+
+test_bench_files = 
+
+

libraries/io/ddr3/hdllib.cfg

+hdl_lib_name = ddr3
+hdl_library_clause_name = ddr3_lib
+hdl_lib_uses_synth = common dp diag diagnostics ss 
+hdl_lib_uses_sim = 
+
+hdl_lib_technology =
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+#modelsim_compile_ip_files =
+#    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
+synth_files =
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_pkg.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_reg.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_seq.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_driver.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_1066.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_800.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_transpose.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3_capture.vhd
+    $UNB/Firmware/modules/ddr3/src/vhdl/seq_ddr3.vhd
+
+test_bench_files = 
+
+modelsim_search_libraries =
+# stratixiv only
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip
+# arria10 only
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
+#    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+#    altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip     twentynm     twentynm_hssi     twentynm_hip
+