Moved digital receiver libraries under applications folder

applications/dig_receiver/designs/dig_receiver_fn/hdllib.cfg

 hdl_lib_name = dig_receiver_fn
 hdl_library_clause_name = dig_receiver_fn_lib
-hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh
+hdl_lib_uses_synth = common mm dp unb1_board diag digital_receiver dr_mesh tr_10GbE_lib dr_udp_packetizer
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = ip_stratixiv

applications/dig_receiver/designs/dig_receiver_fn/src/vhdl/dig_rec_fn.vhd

@@ -49,6 +49,7 @@ LIBRARY common_lib, unb1_board_lib, dp_lib, tse_lib, bf_lib;
 LIBRARY mesh_lib, digrec_lib, common_oa_lib;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
 USE unb1_board_lib.unb1_board_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 --USE tse_lib.tse_pkg.ALL;
@@ -103,8 +104,6 @@ GENERIC (
     SI_FN_2_CNTRL          : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);  -- [2:0]
     SI_FN_RSTN             : OUT   STD_LOGIC;
 	 
-
-
     -- 1GbE Control Interface
     ETH_clk       : IN    STD_LOGIC;
     ETH_SGIN      : IN    STD_LOGIC;
@@ -203,17 +202,26 @@ architecture str of dig_receiver_fn is
   SIGNAL eth10g_udp_miso_arr        : t_mem_miso_arr(2 DOWNTO 0) := (OTHERS=>c_mem_miso_rst);
   SIGNAL eth10g_mac_mosi_arr        : t_mem_mosi_arr(2 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
   SIGNAL eth10g_mac_miso_arr        : t_mem_miso_arr(2 DOWNTO 0) := (OTHERS=>c_mem_miso_rst);
+  SIGNAL reg_xaui_mosi              : t_mem_mosi;
+  SIGNAL reg_xaui_miso              : t_mem_miso;
+  SIGNAL reg_eth10g_mosi            : t_mem_mosi;
+  SIGNAL reg_eth10g_miso            : t_mem_miso;
   SIGNAL eth10g_softreset           : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
 	
   SIGNAL tr_front_clk               : STD_LOGIC;
-  SIGNAL tr_front_serial_out        : STD_LOGIC_VECTOR(11 DOWNTO 0);
-  SIGNAL tr_front_serial_in         : STD_LOGIC_VECTOR(11 DOWNTO 0);
+  --SIGNAL tr_front_serial_out        : STD_LOGIC_VECTOR(11 DOWNTO 0);
+  --SIGNAL tr_front_serial_in         : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL tr_front_phy_mdc           : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL tr_front_phy_mdio_in       : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL tr_front_phy_mdio_out      : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL tr_front_phy_mdio_oen      : STD_LOGIC_VECTOR(2 DOWNTO 0);
   SIGNAL tr_front_rst_n             : STD_LOGIC;
-
+    -- Serial IO
+  SIGNAL i_xaui_tx_arr              : t_xaui_arr(2 DOWNTO 0);
+  SIGNAL i_xaui_rx_arr              : t_xaui_arr(2 DOWNTO 0);
+	     -- Serial XAUI IO
+  SIGNAL tr_front_serial_out        : t_unb1_board_xaui_sl_2arr(2 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+  SIGNAL tr_front_serial_in         : t_unb1_board_xaui_sl_2arr(2 DOWNTO 0);
  -- ADC input
   SIGNAL reg_adc_lvds_mosi     : t_mem_mosi;
   SIGNAL reg_adc_lvds_miso     : t_mem_miso := c_mem_miso_rst;
@@ -548,74 +556,78 @@ stage: ENTITY work.node_dr_2nd_stage
     data_out_siso          => data_out_to_10G_siso
 );
 
---
--- Eth10G front panel link
---
-    tr_front_clk  <= SA_CLK;
-
-    SI_FN_RSTN <= xo_rst_n;
-
-    -- Provide a soft reset for the Eth 10G ports
-    eth10g_mac_rst_n(0) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(0) = '1' ELSE '1';
-    eth10g_mac_rst_n(1) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(1) = '1' ELSE '1';
-    eth10g_mac_rst_n(2) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(2) = '1' ELSE '1';
-
-    -- The MDIO connections to the Vitesse PHY
-    SI_FN_0_CNTRL(1)        <= tr_front_phy_mdc(0);
-    SI_FN_0_CNTRL(2)        <= tr_front_phy_mdio_out(0) WHEN tr_front_phy_mdio_oen(0) = '0' ELSE 'Z';
-    tr_front_phy_mdio_in(0) <= SI_FN_0_CNTRL(2);
-
-    SI_FN_1_CNTRL(1)        <= tr_front_phy_mdc(1);
-    SI_FN_1_CNTRL(2)        <= tr_front_phy_mdio_out(1) WHEN tr_front_phy_mdio_oen(1) = '0' ELSE 'Z';
-    tr_front_phy_mdio_in(1) <= SI_FN_1_CNTRL(2);
-
-    SI_FN_2_CNTRL(1)        <= tr_front_phy_mdc(2);
-    SI_FN_2_CNTRL(2)        <= tr_front_phy_mdio_out(2) WHEN tr_front_phy_mdio_oen(2) = '0' ELSE 'Z';
-    tr_front_phy_mdio_in(2) <= SI_FN_2_CNTRL(2);
-
-    -- Wire fixed 12 transceivers to backplane with 3 bundles of 4 (SI_FN_3 is not used)
-    SI_FN_0_TX(0) <= tr_front_serial_out(0);   tr_front_serial_in(0)  <= SI_FN_0_RX(0);
-    SI_FN_0_TX(1) <= tr_front_serial_out(1);   tr_front_serial_in(1)  <= SI_FN_0_RX(1);
-    SI_FN_0_TX(2) <= tr_front_serial_out(2);   tr_front_serial_in(2)  <= SI_FN_0_RX(2);
-    SI_FN_0_TX(3) <= tr_front_serial_out(3);   tr_front_serial_in(3)  <= SI_FN_0_RX(3);
-    SI_FN_1_TX(0) <= tr_front_serial_out(4);   tr_front_serial_in(4)  <= SI_FN_1_RX(0);
-    SI_FN_1_TX(1) <= tr_front_serial_out(5);   tr_front_serial_in(5)  <= SI_FN_1_RX(1);
-    SI_FN_1_TX(2) <= tr_front_serial_out(6);   tr_front_serial_in(6)  <= SI_FN_1_RX(2);
-    SI_FN_1_TX(3) <= tr_front_serial_out(7);   tr_front_serial_in(7)  <= SI_FN_1_RX(3);
-    SI_FN_2_TX(0) <= tr_front_serial_out(8);   tr_front_serial_in(8)  <= SI_FN_2_RX(0);
-    SI_FN_2_TX(1) <= tr_front_serial_out(9);   tr_front_serial_in(9)  <= SI_FN_2_RX(1);
-    SI_FN_2_TX(2) <= tr_front_serial_out(10);  tr_front_serial_in(10) <= SI_FN_2_RX(2);
-    SI_FN_2_TX(3) <= tr_front_serial_out(11);  tr_front_serial_in(11) <= SI_FN_2_RX(3);
-
 
 link_out: ENTITY work.multi_udp_eth10g_stream
   PORT MAP (
     -- mm interface
     mm_clk          => mm_clk,
-    mm_rst          => eth10g_mm_rst,
+    mm_rst          => mm_rst,
     st_clk          => dp_clk,
     stb_1s          => stb_1s,
-    tpg_mosi_arr    => eth10g_tpg_mosi_arr,
-    tpg_miso_arr    => eth10g_tpg_miso_arr,
     udp_mosi_arr    => eth10g_udp_mosi_arr,
     udp_miso_arr    => eth10g_udp_miso_arr,
-    mac_mosi_arr    => eth10g_mac_mosi_arr,
-    mac_miso_arr    => eth10g_mac_miso_arr,
+    reg_eth10g_mosi => reg_eth10g_mosi,
+    reg_eth10g_miso => reg_eth10g_miso,
+	-- reg_mac_mosi    => reg_mac_mosi,
+	-- reg_mac_miso    => reg_mac_miso,
+	 reg_xaui_mosi   => reg_xaui_mosi,
+	 reg_xaui_miso   => reg_xaui_miso,
 
     -- Transceiver Interface SI-FN via XAUI PHY chips using eth10g
     reconfig_clk    => cal_clk,
-    xaui_rst_n      => eth10g_mac_rst_n,
+    xaui_rst        => xo_rst,
     xaui_xo_clk     => tr_front_clk,
-    xaui_rx         => tr_front_serial_in,
-    xaui_tx         => tr_front_serial_out,
-    phy_mdc         => tr_front_phy_mdc,
-    phy_mdio_in     => tr_front_phy_mdio_in,
-    phy_mdio_out    => tr_front_phy_mdio_out,
-    phy_mdio_oen    => tr_front_phy_mdio_oen,
+    xaui_rx_arr     => i_xaui_rx_arr,
+    xaui_tx_arr     => i_xaui_tx_arr,
 
+    mdio_mdc_arr      => tr_front_phy_mdc,
+    mdio_mdat_in_arr  => tr_front_phy_mdio_in,
+    mdio_mdat_oen_arr => tr_front_phy_mdio_oen,
+    SI_FN_RSTN      => SI_FN_RSTN,
     -- transceiver stream input to links
     tx_sosi         => data_out_to_10G_sosi,
     tx_siso         => data_out_to_10G_siso);
+--
+-- Eth10G front panel link
+--
+    tr_front_clk  <= SA_CLK;
+
+    SI_FN_RSTN <= xo_rst_n;
+    -- Wire together different types
+    gen_wires: FOR i IN 0 TO 2 GENERATE
+      tr_front_serial_out(i) <= i_xaui_tx_arr(i);
+      i_xaui_rx_arr(i) <= tr_front_serial_in(i);
+    END GENERATE;
+	 
+    u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
+    GENERIC MAP (
+      g_nof_xaui => 3
+    )
+    PORT MAP (
+      xaui_tx_arr       => tr_front_serial_out,
+      xaui_rx_arr       => tr_front_serial_in,
+
+      mdio_mdc_arr      => tr_front_phy_mdc,
+      mdio_mdat_in_arr  => tr_front_phy_mdio_in,
+      mdio_mdat_oen_arr => tr_front_phy_mdio_oen,
+
+      -- Serial I/O
+      SI_FN_0_TX        => SI_FN_0_TX,
+      SI_FN_0_RX        => SI_FN_0_RX,
+      SI_FN_1_TX        => SI_FN_1_TX,
+      SI_FN_1_RX        => SI_FN_1_RX,
+      SI_FN_2_TX        => SI_FN_2_TX,
+      SI_FN_2_RX        => SI_FN_2_RX,
+
+      SI_FN_0_CNTRL     => SI_FN_0_CNTRL,
+      SI_FN_1_CNTRL     => SI_FN_1_CNTRL,
+      SI_FN_2_CNTRL     => SI_FN_2_CNTRL
+     -- SI_FN_3_CNTRL     => SI_FN_3_CNTRL
+    );
+    -- Provide a soft reset for the Eth 10G ports
+    eth10g_mac_rst_n(0) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(0) = '1' ELSE '1';
+    eth10g_mac_rst_n(1) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(1) = '1' ELSE '1';
+    eth10g_mac_rst_n(2) <= '0' WHEN xo_rst_n = '0' OR eth10g_softreset(2) = '1' ELSE '1';
 
   -- Generate 1 cycle pps and ms pulses
   -- pps led can be used for a front panel activity LED

applications/dig_receiver/libraries/udp_packetizer/hdllib.cfg

 hdl_lib_name = dr_udp_packetizer
 hdl_library_clause_name = dr_udp_packetizer_lib
-hdl_lib_uses_synth = common mm dp technlolgy tech_mac_10g
+hdl_lib_uses_synth = common mm dp technology_lib tr_10GbE_lib tech_mac_10g tech_eth_10g tr_xaui
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 
@@ -9,14 +9,10 @@ build_dir_sim = $HDL_BUILD_DIR
 build_dir_synth = $HDL_BUILD_DIR
 
 synth_files =
-    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/digrec_pkg.vhd
-   
-udp_formatter.vhd
-udp_packetizer_pkg.vhd
-udp_packetizer_st.vhd
-unb_packetizer_tpg.vhd
-udp_eth10g_stream.vhd
-multi_udp_eth10g_stream.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_pkg.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_packetizer_st.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/udp_eth10g_stream.vhd
+    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/udp_packetizer/src/vhdl/multi_udp_eth10g_stream.vhd
 
 test_bench_files = 
 

applications/dig_receiver/libraries/vdif_formatter/hdllib.cfg

@@ -12,7 +12,6 @@ synth_files =
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/format_header.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter_mm.vhd
-    $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter_mm_hw.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/formatter_word_pack.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/frame_fifo_ip.vhd
     $SVN/Digital_Receiver/trunk/Firmware/modules_HDL/formatter/src/vhdl/ip_checksum.vhd