quartus assignment tries

boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl

@@ -19,6 +19,7 @@ set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to PPS
 
 # IO Standard Assignments from Gijs (excluding memory)
 set_instance_assignment -name IO_STANDARD "1.8 V" -to ETH_CLK
+#set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ETH_CLK
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[0]
 set_instance_assignment -name IO_STANDARD LVDS -to "ETH_SGIN[0](n)"
 set_instance_assignment -name IO_STANDARD LVDS -to ETH_SGIN[1]

boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf

@@ -118,3 +118,9 @@ if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
   set_parameter -name g_stamp_svn [regsub -all {[^0-9]} [exec echo $::env(RADIOHDL_SVN_REVISION)] ""] 
 }
 
+#set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_tx_d"
+#set_instance_assignment -name FAST_INPUT_REGISTER ON -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tbi_rx_d"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|tx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|rx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_pcs_pma_nf_lvds:i_tse_pcs_0|rx_clk"
+#set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to "ctrl_unb2_board:u_ctrl|eth:\\gen_eth:u_eth|tech_tse:u_tech_tse|tech_tse_arria10_e3sge3:\\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_tse_sgmii_lvds:\\u_LVDS_tse:u_tse|ip_arria10_e3sge3_tse_sgmii_lvds_altera_eth_tse_151_6kz2wlq:eth_tse_0|altera_eth_tse_mac:i_tse_mac|tx_clk"

boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc

@@ -45,9 +45,9 @@ derive_clock_uncertainty
 
 
 # False path the PPS to DDIO:
-set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e3sge3:u0|xcvr_fpll_a10_0|outclk0}] 3.5 [get_ports {PPS}]
+set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e3sge3:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
 set_false_path -from {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e3sge3_ddio_in:\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_ddio_in_1:\gen_w:0:u_ip_arria10_e3sge3_ddio_in_1|ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr__nff} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap_NEW_REG0}; set_false_path -from {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e3sge3_ddio_in:\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_ddio_in_1:\gen_w:0:u_ip_arria10_e3sge3_ddio_in_1|ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr__nff} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap_NEW_REG*}
-
+set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e3sge3_ddio_in:\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_ddio_in_1:\gen_w:0:u_ip_arria10_e3sge3_ddio_in_1|ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr__nff}; set_false_path -from {PPS} -to {ctrl_unb2_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e3sge3_ddio_in:\gen_ip_arria10_e3sge3:u0|ip_arria10_e3sge3_ddio_in_1:\gen_w:0:u_ip_arria10_e3sge3_ddio_in_1|ip_arria10_e3sge3_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr__nff}