Corrected verify_no_bg_buffer_ram_en and verify_tx_seq_en to verify g_use_tx_seq.

libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd

@@ -41,14 +41,14 @@ USE work.diag_pkg.ALL;
 
 ENTITY tb_mms_diag_block_gen IS
   GENERIC (
-    g_use_usr_input        : BOOLEAN := TRUE;
-    g_use_bg               : BOOLEAN := FALSE;
+    g_use_usr_input        : BOOLEAN := FALSE;
+    g_use_bg               : BOOLEAN := TRUE;
     g_use_tx_seq           : BOOLEAN := TRUE;
-    g_use_bg_buffer_ram    : BOOLEAN := TRUE;
+    g_use_bg_buffer_ram    : BOOLEAN := FALSE;
     g_usr_bypass_xonoff    : BOOLEAN := FALSE;
-    g_flow_control_verify  : t_dp_flow_control_enum := e_random;  -- always active, or random flow control
+    g_flow_control_verify  : t_dp_flow_control_enum := e_active;  -- always active, or random flow control
     g_nof_repeat           : NATURAL := 5;
-    g_nof_streams          : NATURAL := 2;
+    g_nof_streams          : NATURAL := 1;
     g_gap_size             : NATURAL := 0
   );
 END tb_mms_diag_block_gen;
@@ -425,7 +425,7 @@ BEGIN
   END PROCESS;
   
   verify_tx_seq_en           <= '1' WHEN verify_data_en='1' AND g_use_tx_seq=TRUE                                ELSE '0';
-  verify_no_bg_buffer_ram_en <= '1' WHEN verify_data_en='1' AND g_use_bg_buffer_ram=FALSE ELSE '0';
+  verify_no_bg_buffer_ram_en <= '1' WHEN verify_data_en='1' AND g_use_tx_seq=FALSE AND g_use_bg_buffer_ram=FALSE ELSE '0';
   
   proc_dp_verify_data("Tx sequence counter data",                   0, 0, clk, verify_tx_seq_en,           out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u0);
   proc_dp_verify_data("No BG buffer RAM counter data", c_block_size-1, 0, clk, verify_no_bg_buffer_ram_en, out_sosi_0.valid, out_sosi_0_data, prev_out_sosi_0_data_u1);