Transmit packets without gap in between.

libraries/technology/mac_10g/tb_tech_mac_10g.vhd

@@ -89,11 +89,11 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
   SIGNAL mm_rst            : STD_LOGIC;         -- reset synchronous with mm_clk
   SIGNAL clk_312           : STD_LOGIC := '1';  -- 312.5  MHz
   SIGNAL clk_156           : STD_LOGIC := '0';  -- 156.25 MHz
-  SIGNAL tx_ref_clk_312    : STD_LOGIC := '1';  -- mac_10g
-  SIGNAL tx_ref_clk_156    : STD_LOGIC := '0';  -- mac_10g reference clock
+  SIGNAL tx_ref_clk_312    : STD_LOGIC := '1';
+  SIGNAL tx_ref_clk_156    : STD_LOGIC := '0';
   SIGNAL tx_rst            : STD_LOGIC;         -- reset synchronous with tx_ref_clk_156
-  SIGNAL rx_phy_clk_312    : STD_LOGIC := '1';  -- mac_10g
-  SIGNAL rx_phy_clk_156    : STD_LOGIC := '0';  -- mac_10g rx clock from phy = tx_ref_clk_156 in this tb
+  SIGNAL rx_phy_clk_312    : STD_LOGIC := '1';
+  SIGNAL rx_phy_clk_156    : STD_LOGIC := '0';
   SIGNAL rx_rst            : STD_LOGIC;         -- reset synchronous with rx_phy_clk_156 = tx_ref_clk_156 in this tb
 
   -- 10G MAC control interface
@@ -132,7 +132,6 @@ ARCHITECTURE tb OF tb_tech_mac_10g IS
   
 BEGIN
 
-  -- run 50 us
   mm_clk  <= NOT mm_clk  OR tb_end AFTER mm_clk_period/2;   -- MM clock
   clk_156 <= NOT clk_156 OR tb_end AFTER clk_156_period/2;
   clk_312 <= NOT clk_312 OR tb_end AFTER clk_156_period/4;
@@ -193,7 +192,7 @@ BEGIN
     
     FOR I IN 0 TO c_nof_pkt-1 LOOP
       proc_tech_mac_10g_tx_packet(total_header, c_pkt_length_arr(I), g_data_type, c_rl, c_nof_tx_not_valid, tx_ref_clk_156, tx_en, tx_siso, tx_sosi);
-      proc_common_wait_some_cycles(tx_ref_clk_156, 10);
+      proc_common_wait_some_cycles(tx_ref_clk_156, 0);
     END LOOP;
 
     proc_common_wait_some_cycles(tx_ref_clk_156, c_pkt_length_arr(c_nof_pkt-1)/c_tech_mac_10g_symbols_per_beat);
@@ -286,7 +285,7 @@ BEGIN
       tx_snk_out        => tx_siso, 
       
       rx_clk_312        => rx_phy_clk_312,
-      rx_clk_156        => rx_phy_clk_156, -- 156.25 MHz from rx phy
+      rx_clk_156        => rx_phy_clk_156, -- 156.25 MHz from local reference or from rx phy (dependent on g_technology)
       rx_rst            => rx_rst,
       rx_src_out        => rx_sosi,        -- 64 bit data
       rx_src_in         => rx_siso,