Added support for pipelining the MM bus, no need for multi tb_tb, because...

Added support for pipelining the MM bus, no need for multi tb_tb, because default no pipelining is sufficient for tb.

libraries/base/common/tb/vhdl/tb_common_mem_master_mux.vhd

@@ -52,9 +52,11 @@ USE work.tb_common_mem_pkg.ALL;
 
 ENTITY tb_common_mem_master_mux IS
  GENERIC (
-    g_nof_masters    : POSITIVE := 2;   -- Number of master memory interfaces on the MM bus array.
-    g_base_arr       : t_nat_natural_arr := (0, 256);  -- Address base per slave port of common_mem_bus
-    g_width_arr      : t_nat_natural_arr := (4,   8)   -- Address width per slave port of common_mem_bus
+    g_nof_masters       : POSITIVE := 2;   -- Number of master memory interfaces on the MM bus array.
+    g_base_arr          : t_nat_natural_arr := (0, 256);  -- Address base per slave port of common_mem_bus
+    g_width_arr         : t_nat_natural_arr := (4,   8);  -- Address width per slave port of common_mem_bus
+    g_pipeline_bus_mosi : BOOLEAN := FALSE;
+    g_pipeline_bus_miso : BOOLEAN := FALSE
   );
 END tb_common_mem_master_mux;
 
@@ -67,12 +69,16 @@ ARCHITECTURE tb OF tb_common_mem_master_mux IS
 
   CONSTANT mm_clk_period   : TIME    := 10 ns;
   
-  CONSTANT c_rd_latency      : NATURAL := 1; 
-  CONSTANT c_rd_latency_arr  : t_nat_natural_arr := array_init(c_rd_latency, g_nof_masters);
-  CONSTANT c_rd_latency_min  : NATURAL := smallest(c_rd_latency_arr);
+  CONSTANT c_bus_mosi_latency   : NATURAL := sel_a_b(g_pipeline_bus_mosi, 1, 0);
+  CONSTANT c_bus_miso_latency   : NATURAL := sel_a_b(g_pipeline_bus_miso, 1, 0);
+  CONSTANT c_ram_rd_latency     : NATURAL := 1; 
+  CONSTANT c_ram_rd_latency_arr : t_nat_natural_arr := array_init(c_ram_rd_latency, g_nof_masters);
+  
+  CONSTANT c_read_latency    : NATURAL := c_bus_mosi_latency + c_ram_rd_latency + c_bus_miso_latency;
+
   CONSTANT c_addr_w          : NATURAL := largest(ceil_log2(largest(g_base_arr)), largest(g_width_arr)) + 1;
   CONSTANT c_data_w          : NATURAL := 32;
-  CONSTANT c_test_ram        : t_c_mem := (latency  => c_rd_latency,
+  CONSTANT c_test_ram        : t_c_mem := (latency  => c_ram_rd_latency,
                                            adr_w    => c_addr_w,
                                            dat_w    => c_data_w,
                                            nof_dat  => 2**c_addr_w,
@@ -122,7 +128,7 @@ BEGIN
         v_span := 2**g_width_arr(I);
         FOR J IN v_span-1 DOWNTO 0 LOOP
           proc_mem_mm_bus_rd(v_base + J, mm_clk, stimuli_mosi);
-          proc_common_wait_some_cycles(mm_clk, c_rd_latency);
+          proc_common_wait_some_cycles(mm_clk, c_read_latency);
           v_data := TO_UINT(stimuli_miso.rddata(31 DOWNTO 0));
           IF v_data /= R+J THEN
             REPORT "Error! Readvalue is not as expected" SEVERITY ERROR;
@@ -142,9 +148,9 @@ BEGIN
     g_nof_slaves      => g_nof_masters,
     g_base_arr        => g_base_arr,
     g_width_arr       => g_width_arr,
-    g_rd_latency_arr  => c_rd_latency_arr,
-    g_pipeline_mosi   => FALSE,
-    g_pipeline_miso   => FALSE
+    g_rd_latency_arr  => c_ram_rd_latency_arr,
+    g_pipeline_mosi   => g_pipeline_bus_mosi,
+    g_pipeline_miso   => g_pipeline_bus_miso
   )
   PORT MAP (
     mm_clk         => mm_clk,
@@ -158,7 +164,7 @@ BEGIN
   u_dut: ENTITY work.common_mem_master_mux
   GENERIC MAP (
     g_nof_masters     => g_nof_masters,
-    g_rd_latency_min  => c_rd_latency_min
+    g_rd_latency_min  => c_read_latency
   )
   PORT MAP (
     mm_clk          => mm_clk,