Add 10GbE output and IQUV TABs output module for ARTS sc4

applications/arts/designs/arts_unb1_sc4/hdllib.cfg

 hdl_lib_name = arts_unb1_sc4
 hdl_library_clause_name = arts_unb1_sc4_lib
-hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board iquv wpfb filter rTwoSDF apertif_unb1_correlator
+hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board arts_tab_beamformer iquv wpfb filter rTwoSDF apertif_unb1_correlator
 hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
 hdl_lib_technology = ip_stratixiv
 
@@ -9,7 +9,7 @@ synth_files =
     src/vhdl/arts_unb1_sc4_input.vhd
     src/vhdl/arts_unb1_sc4_processing.vhd
 
-    src/vhdl/arts_unb1_sc4_output_tab_iquv_reorder.vhd
+    src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
     src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
     src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
     src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd

@@ -164,6 +164,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
 
   SIGNAL arts_unb1_sc4_output_tab_src_out    : t_dp_sosi;
   SIGNAL arts_unb1_sc4_output_tab_src_in     : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL dummy_src_in_arr                    : t_dp_siso_arr(1 DOWNTO 0);
 
   SIGNAL arts_unb1_sc4_output_iab_src_out_arr    : t_dp_sosi_arr(0 DOWNTO 0);
   SIGNAL arts_unb1_sc4_output_iab_src_in_arr     : t_dp_siso_arr(0 DOWNTO 0) := (others => c_dp_siso_rdy);
@@ -307,6 +308,11 @@ BEGIN
     reg_dp_bsn_monitor_mesh_mosi       =>  reg_dp_bsn_monitor_mesh_mosi,   
     reg_dp_bsn_monitor_mesh_miso       =>  reg_dp_bsn_monitor_mesh_miso,   
 
+    tr_10GbE_tx_snk_in_arr(2 DOWNTO 1) => (OTHERS => c_dp_sosi_rst),
+    tr_10GbE_tx_snk_in_arr(0)          => arts_unb1_sc4_output_tab_src_out,
+    tr_10GbE_tx_snk_out_arr(2 DOWNTO 1)=> dummy_src_in_arr,
+    tr_10GbE_tx_snk_out_arr(0)         => arts_unb1_sc4_output_tab_src_in,
+ 
     src_out_arr => arts_unb1_sc4_input_src_out_arr,
     general_bsn => general_bsn
   );

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_input.vhd

@@ -97,6 +97,9 @@ ENTITY arts_unb1_sc4_input IS
     reg_dp_bsn_monitor_mesh_mosi       : IN  t_mem_mosi := c_mem_mosi_rst;   
     reg_dp_bsn_monitor_mesh_miso       : OUT t_mem_miso := c_mem_miso_rst;   
 
+    tr_10GbE_tx_snk_out_arr            : OUT t_dp_siso_arr(2 DOWNTO 0);
+    tr_10GbE_tx_snk_in_arr             : IN  t_dp_sosi_arr(2 DOWNTO 0);
+
     src_out_arr     : OUT t_dp_sosi_arr(12-1 DOWNTO 0);
     general_bsn     : OUT std_logic_vector(63 DOWNTO 0) := (others => '0')
   );
@@ -281,6 +284,9 @@ BEGIN
     dp_rst            => dp_rst,
     dp_clk            => dp_clk,
   
+    snk_out_arr       => tr_10GbE_tx_snk_out_arr,
+    snk_in_arr        => tr_10GbE_tx_snk_in_arr,
+  
     src_out_arr       => dp_offload_rx_snk_in_arr,
     src_in_arr        => dp_offload_rx_snk_out_arr,
   

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd

@@ -102,7 +102,8 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab IS
   SIGNAL arts_unb1_sc4_output_i_packetizer_src_out    : t_dp_sosi;
   SIGNAL arts_unb1_sc4_output_i_packetizer_src_in     : t_dp_siso;
 
-  SIGNAL arts_unb1_sc4_output_iquv_reorder_src_out_arr   : t_dp_sosi_arr(g_nof_compound_beams-1 DOWNTO 0);
+  SIGNAL arts_unb1_sc4_output_iquv_buffer_src_out     : t_dp_sosi;
+  SIGNAL arts_unb1_sc4_output_iquv_buffer_src_in      : t_dp_siso;
 
   SIGNAL arts_unb1_sc4_output_iquv_packetizer_src_out : t_dp_sosi;
   SIGNAL arts_unb1_sc4_output_iquv_packetizer_src_in  : t_dp_siso;
@@ -186,30 +187,30 @@ BEGIN
 
 
   -----------------------------------------------------------------------------
-  -- IQUV reorder
+  -- IQUV buffer
   -----------------------------------------------------------------------------
-  u_arts_unb1_sc4_output_iquv_reorder: ENTITY work.arts_unb1_sc4_output_iquv_reorder
+  u_arts_unb1_sc4_output_tab_iquv_buffer: ENTITY work.arts_unb1_sc4_output_tab_iquv_buffer
   GENERIC MAP(
     g_nof_tabs                => g_nof_tabs,
-    g_nof_compound_beams   => g_nof_compound_beams,
-    g_nof_stokes           => 4, --IQUV
-    g_nof_bytes_per_packet => g_nof_bytes_per_iquv_packet,
-    g_nof_channels         => g_nof_channels
+    g_nof_bytes_per_packet    => g_nof_bytes_per_iquv_packet
   )
   PORT MAP(
     dp_clk      => dp_clk,
     dp_rst      => dp_rst,
 
     snk_in_arr  => snk_in_arr,
-    src_out_arr => arts_unb1_sc4_output_iquv_reorder_src_out_arr
+    src_out     => arts_unb1_sc4_output_iquv_buffer_src_out,
+    src_in      => arts_unb1_sc4_output_iquv_buffer_src_in
   );
 
   -----------------------------------------------------------------------------
-  -- IQUV packetizer with internal BG
+  -- IQUV packetizer with internal BG and fill fifo
   -----------------------------------------------------------------------------
-  u_arts_unb1_sc4_output_iquv_packetizer: ENTITY work.arts_unb1_sc4_output_iquv_packetizer
+  u_arts_unb1_sc4_output_tab_iquv_packetizer: ENTITY work.arts_unb1_sc4_output_tab_iquv_packetizer
   GENERIC MAP(
     g_sim                         => g_sim,
+    g_use_block_generator         => FALSE,
+    g_nof_tabs                    => g_nof_tabs,
     g_nof_bytes_per_packet        => g_nof_bytes_per_iquv_packet
   )
   PORT MAP(
@@ -225,7 +226,10 @@ BEGIN
     reg_dp_xonoff_mosi             => reg_dp_xonoff_iquv_mosi,
     reg_dp_xonoff_miso             => reg_dp_xonoff_iquv_miso,
 
-    snk_in                         => arts_unb1_sc4_output_iquv_reorder_src_out_arr(0),
+    general_bsn                    => general_bsn,
+
+    snk_in                         => arts_unb1_sc4_output_iquv_buffer_src_out,
+    snk_out                        => arts_unb1_sc4_output_iquv_buffer_src_in,
  
     src_out                        => arts_unb1_sc4_output_iquv_packetizer_src_out,
     src_in                         => arts_unb1_sc4_output_iquv_packetizer_src_in,

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd

@@ -170,6 +170,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
   SIGNAL id_band                      : STD_LOGIC_VECTOR(  c_byte_w-1 DOWNTO 0);
   SIGNAL id_channel                   : STD_LOGIC_VECTOR(2*c_byte_w-1 DOWNTO 0);
   SIGNAL id_cb                        : STD_LOGIC_VECTOR(  c_byte_w-1 DOWNTO 0);
+  SIGNAL id_tab                       : STD_LOGIC_VECTOR(  c_byte_w-1 DOWNTO 0);
   SIGNAL id_sequence_number           : STD_LOGIC_VECTOR(  c_byte_w-1 DOWNTO 0);
   SIGNAL id_local_channel             : STD_LOGIC_VECTOR(6 DOWNTO 0);
   SIGNAL id_udp_dst_prt               : STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -184,10 +185,9 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS
   SIGNAL dp_counter_count_src_out_arr : t_dp_sosi_arr(4 DOWNTO 0);
   SIGNAL dp_counter_src_out_cb        : STD_LOGIC_VECTOR( 2 DOWNTO 0);
   SIGNAL dp_counter_src_out_sb        : STD_LOGIC_VECTOR( 4 DOWNTO 0);
+  SIGNAL dp_counter_src_out_seq       : STD_LOGIC_VECTOR( 5 DOWNTO 0);
   SIGNAL dp_counter_src_out_tab       : STD_LOGIC_VECTOR( 3 DOWNTO 0);
-  SIGNAL dp_counter_src_out_seq       : STD_LOGIC_VECTOR( 1 DOWNTO 0);
   SIGNAL dp_counter_src_out_ch        : STD_LOGIC_VECTOR( 1 DOWNTO 0);
-  SIGNAL dp_counter_src_out_t         : STD_LOGIC_VECTOR(12 DOWNTO 0);
 
   SIGNAL general_bsn_latched          : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
   SIGNAL capture_initial_bsn          : STD_LOGIC := '1';
@@ -272,9 +272,9 @@ BEGIN
   -- . [CBxSB 0..87(119)][SEQ 0..3][TAB 0..11][CH 0..3][t 0..6249]
   --   . c0 = range(0,g_nof_bytes_per_packet,1) t
   --   . c1 = range(0,4,1) CH
-  --   . c2 = range(0,12,1) TAB
-  --   . c3 = range(0,3,1) SEQ
-  --   . c4 = range(0,88,1) CB x SB, then extract the CB and SB
+  --   . c1 = range(0,12,1) TAB
+  --   . c2 = range(0,4,1) SEQ
+  --   . c3 = range(0,88,1) CB x SB, then extract the CB and SB
   ----------------------------------------------------------------------------- 
   u_dp_counter : ENTITY dp_lib.dp_counter
   GENERIC MAP (
@@ -354,10 +354,9 @@ BEGIN
 
   dp_counter_src_out_sb(2 downto 0) <= dp_counter_count_src_out_arr(4).data(2 downto 0);
 
-  dp_counter_src_out_seq <= dp_counter_count_src_out_arr(3).data( 1 DOWNTO 0);
+  dp_counter_src_out_seq <= dp_counter_count_src_out_arr(3).data( 5 DOWNTO 0);
   dp_counter_src_out_tab <= dp_counter_count_src_out_arr(2).data( 3 DOWNTO 0);
   dp_counter_src_out_ch  <= dp_counter_count_src_out_arr(1).data( 1 DOWNTO 0);
-  dp_counter_src_out_t   <= dp_counter_count_src_out_arr(0).data(12 DOWNTO 0);
 
   -- Latch the bsn at the start and when the dp_counter rolls over
 
@@ -368,7 +367,7 @@ BEGIN
       capture_initial_bsn <= '1';
     ELSE
       IF rising_edge(dp_clk) THEN
-        IF dp_counter_count_src_out_arr(3).eop = '1' or capture_initial_bsn = '1' THEN
+        IF dp_counter_count_src_out_arr(4).eop = '1' or capture_initial_bsn = '1' THEN
           general_bsn_latched <= general_bsn;
         END IF;
         IF capture_initial_bsn = '1' and dp_counter_count_src_out_arr(3).sop = '1' THEN
@@ -379,11 +378,11 @@ BEGIN
   END PROCESS;
 
   -- Channels 0..3 and Subbands 0..23 are combined into local FPGA channels 0..95.
-  id_local_channel <= dp_counter_src_out_sb & dp_counter_src_out_ch; -- Assignment of global channel index
+  id_local_channel <= dp_counter_src_out_sb & dp_counter_src_out_ch; -- The 4 post integration channels are combined in a packet
 
   -- We'll carry all relevant indices in the DP channel field.
-  dp_xonoff_snk_in.channel(31 DOWNTO 12) <= (OTHERS=>'0');
-  dp_xonoff_snk_in.channel(11 DOWNTO  0) <= dp_counter_src_out_cb & id_local_channel & dp_counter_src_out_seq;
+  dp_xonoff_snk_in.channel(31 DOWNTO 20) <= (OTHERS=>'0');
+  dp_xonoff_snk_in.channel(19 DOWNTO  0) <= dp_counter_src_out_tab & dp_counter_src_out_cb & id_local_channel & dp_counter_src_out_seq;
 
   -- Use the min/max pulses of the fastest dimension to tag SOP/EOP so we get g_packetsize Byte packets
   dp_xonoff_snk_in.sop   <= dp_counter_count_src_out_arr(0).sop; --FIXME This is only required when using block gen
@@ -431,7 +430,7 @@ BEGIN
   -----------------------------------------------------------------------------
   u_dp_demux : ENTITY dp_lib.dp_demux
   GENERIC MAP (
-    g_mode              => 1,       -- Use EOP to select next input
+    g_mode              => 2,       -- Use sel ctrl
     g_combined          => FALSE,   -- Only the current channel needs to be ready
     g_nof_output        => c_nof_offloadstreams,
     g_remove_channel_lo => FALSE 
@@ -440,6 +439,8 @@ BEGIN
     clk         => dp_clk,
     rst         => dp_rst,
 
+    sel_ctrl    => TO_UINT(dp_xonoff_src_out.channel(15 DOWNTO 13)), -- Field that contains the 3 bits needed to encode beam index 0..4
+
     snk_in      => dp_xonoff_src_out, 
     snk_out     => dp_xonoff_src_in, 
 
@@ -495,11 +496,13 @@ BEGIN
   id_channel_offset <= sel_n(TO_UINT(id_band(2 DOWNTO 0)) , 0, 96, 192, 288, 384, 480, 576, 672) + sel_a_b(TO_UINT(id_band(3 DOWNTO 3)), 768, 0);
 
   -- Combine local channel index 0..95 with the UniBoard/band ID 0..15 to get global channels 0..1535.
-  id_channel         <= TO_UVEC(id_channel_offset + TO_UINT(dp_xonoff_src_out.channel(8 DOWNTO 2)), 16);
+  id_channel         <= TO_UVEC(id_channel_offset + TO_UINT(dp_xonoff_src_out.channel(12 DOWNTO 6)), 16);
   -- Combine local CB index 0..4 with the FPGA ID 0..7 to get global CB indices 0..39.
-  id_cb              <= TO_UVEC(id_cb_offset + TO_UINT(dp_xonoff_src_out.channel(11 DOWNTO 9)),  8);
+  id_cb              <= TO_UVEC(id_cb_offset + TO_UINT(dp_xonoff_src_out.channel(15 DOWNTO 13)),  8);
   -- The sequence number 0..3
-  id_sequence_number <= RESIZE_UVEC(dp_xonoff_src_out.channel(1 DOWNTO 0), c_byte_w);
+  id_sequence_number <= RESIZE_UVEC(dp_xonoff_src_out.channel(5 DOWNTO 0), c_byte_w);
+  -- The tab 0..11
+  id_tab             <= RESIZE_UVEC(dp_xonoff_src_out.channel(19 DOWNTO 16), c_byte_w);
   id_udp_dst_prt     <= TO_UVEC(c_udp_dst_prt_base + TO_UINT(id_cb), 16); 
 
   --------------------------------------------------------------------------------------- 
@@ -515,10 +518,13 @@ BEGIN
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_channel_index"  ) DOWNTO field_lo(c_hdr_field_arr, "id_channel_index"  )) <= id_channel;
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_cb_index"       ) DOWNTO field_lo(c_hdr_field_arr, "id_cb_index"       )) <= id_cb; 
     hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_sequence_number") DOWNTO field_lo(c_hdr_field_arr, "id_sequence_number")) <= id_sequence_number; 
+    hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_tab_index"      ) DOWNTO field_lo(c_hdr_field_arr, "id_tab_index"      )) <= id_tab; 
   END GENERATE;
 
   -----------------------------------------------------------------------------
   -- dp_mux the 5 streams into a single stream again
+  -- TODO: better to pass the channel through dp_concat_field_blk
+  -- TODO: save resources by not muxing the data
   -----------------------------------------------------------------------------
   u_mux : ENTITY dp_lib.dp_mux
   GENERIC MAP (
@@ -526,7 +532,7 @@ BEGIN
     g_empty_w         => c_empty_w,
     g_use_empty       => TRUE,
     g_error_w         => 1,
-    g_mode            => 1, -- forced round robin mode
+    g_mode            => 2, -- use sel ctrl input
     g_nof_input       => c_nof_offloadstreams,
     g_fifo_size       => array_init(1024, c_nof_offloadstreams),  -- FIFO is not used, but generic must match g_nof_input
     g_fifo_fill       => array_init(0, c_nof_offloadstreams)   -- FIFO is not used, but generic must match g_nof_input
@@ -534,6 +540,9 @@ BEGIN
   PORT MAP (
     rst         => dp_rst,
     clk         => dp_clk,
+
+    sel_ctrl    => TO_UINT(dp_xonoff_src_out.channel(15 DOWNTO 13)), -- Field that contains the 3 bits needed to encode beam index 0..4
+
     -- ST sinks
     snk_out_arr => dp_field_blk_src_in_arr,  
     snk_in_arr  => dp_field_blk_src_out_arr,

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd

@@ -159,8 +159,8 @@ BEGIN
 
 
   gen_reordering_fifos : FOR tabno IN 0 TO g_nof_tabs-1 GENERATE
-    dp_deinterleave_snk_in_arr(tabno).empty <= (others => '0');
-    dp_deinterleave_snk_in_arr(tabno).err <= (others => '0');
+--    dp_deinterleave_snk_in_arr(tabno).empty <= (others => '0');
+--    dp_deinterleave_snk_in_arr(tabno).err <= (others => '0');
 
     -----------------------------------------------------------------------------
     -- Deinterleave snk_in into 4 (channel) substreams

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2017
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author:
+-- . Daniel van der Schuur
+-- Purpose:
+-- . TAB buffer and multiplex stage
+-- Description:
+-- . Input : 12 TAB streams carrying 5CB each
+-- . Output: Single stream
+
+
+LIBRARY IEEE, common_lib, work, technology_lib, mm_lib, unb1_board_lib, dp_lib, tech_tse_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY arts_unb1_sc4_output_tab_iquv_buffer IS
+  GENERIC (
+    g_nof_tabs                : NATURAL;
+    g_nof_bytes_per_packet    : NATURAL
+  ); 
+  PORT (
+    dp_rst      : IN  STD_LOGIC;
+    dp_clk      : IN  STD_LOGIC;  
+
+    snk_in_arr  : IN  t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- 12 TAB streams
+
+    src_out     : OUT t_dp_sosi;
+    src_in      : IN  t_dp_siso
+  );
+END arts_unb1_sc4_output_tab_iquv_buffer;
+
+
+ARCHITECTURE str OF arts_unb1_sc4_output_tab_iquv_buffer IS
+
+  CONSTANT c_nof_stokes           : NATURAL := 4;
+  CONSTANT c_indata_w             : NATURAL := c_byte_w * c_nof_stokes;
+  CONSTANT c_data_w               : NATURAL := c_indata_w * 2;
+  CONSTANT c_empty_w              : NATURAL := ceil_log2(c_data_w /c_byte_w);
+  CONSTANT c_nof_fifos            : NATURAL := g_nof_tabs;
+
+  CONSTANT c_nof_words_per_packet : NATURAL := g_nof_bytes_per_packet/(c_indata_w/c_byte_w);
+  CONSTANT c_dp_fifo_sc_size      : NATURAL := 1600; --8192/8; 
+  CONSTANT c_dp_channel_w         : NATURAL := 4*c_byte_w; --4 bytes: TAB, CB, Subband, Channel index.
+
+  SIGNAL dp_counter_data_src_out_arr      : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
+  SIGNAL dp_repack_snk_in_arr             : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
+  SIGNAL dp_fifo_sc_snk_in_arr            : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
+  SIGNAL dp_fifo_sc_src_out_arr           : t_dp_sosi_arr(0 TO g_nof_tabs-1); 
+  SIGNAL dp_fifo_sc_src_in_arr            : t_dp_siso_arr(0 TO g_nof_tabs-1); 
+  SIGNAL dp_pipeline_ready_src_out_arr    : t_dp_sosi_arr(0 TO g_nof_tabs-1); 
+  SIGNAL dp_pipeline_ready_src_in_arr     : t_dp_siso_arr(0 TO g_nof_tabs-1); 
+  SIGNAL dp_counter_count_src_out_arr     : t_dp_sosi_arr(0 DOWNTO 0); 
+  SIGNAL dp_mux_src_in                    : t_dp_siso; 
+
+  SIGNAL end_of_packet                    : STD_LOGIC;
+  SIGNAL end_of_packet_latched            : STD_LOGIC;
+
+BEGIN
+
+
+  -----------------------------------------------------------------------------
+  -- Use dp_counter to generate IQUV packet boundaries
+  -- . For now assume that all TABS (and IAB if used) are syncronized so that we can
+  -- . reference the count off TAB(0) 
+  -----------------------------------------------------------------------------
+  -- . [t 0..g_packetsize-1]
+  -- . Typical values for SC4 are:
+  --   . c0 = range(0,2000,1) t
+  ----------------------------------------------------------------------------- 
+  u_dp_counter : ENTITY dp_lib.dp_counter
+  GENERIC MAP (
+    g_nof_counters => 1,       
+    g_range_start  => (0,0,0,0,0,0,0,0,0, 0),
+    g_range_stop   => (0,0,0,0,0,0,0,0,0, c_nof_words_per_packet),
+    g_range_step   => (0,0,0,0,0,0,0,0,0, 1),
+    g_pipeline_src_out => 1,
+    g_pipeline_src_in  => 0
+  )
+  PORT MAP (
+    rst       => dp_rst,
+    clk       => dp_clk,
+
+    snk_in    => snk_in_arr(0),
+    src_out   => dp_counter_data_src_out_arr(0),
+
+    count_src_out_arr => dp_counter_count_src_out_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Delay the other TABs to match the latency of the dp_counter
+  -----------------------------------------------------------------------------
+  gen_pipeline_i : IF g_nof_tabs > 1 GENERATE
+    u_pipeline_i : ENTITY dp_lib.dp_pipeline_arr
+      GENERIC MAP(
+        g_nof_streams   => g_nof_tabs-1,
+        g_pipeline      => 1 
+      )
+      PORT MAP(
+        rst             => dp_rst,
+        clk             => dp_clk,
+        snk_in_arr      => snk_in_arr(g_nof_tabs-1 DOWNTO 1),
+        src_out_arr     => dp_counter_data_src_out_arr(g_nof_tabs-1 DOWNTO 1)
+      );
+  END GENERATE;
+
+
+
+  gen_buffering_fifos : FOR tabno IN 0 TO g_nof_tabs-1 GENERATE
+
+    -----------------------------------------------------------------------------
+    -- Feed each channel stream into a dp_fifo_sc
+    -- The empty fields of the incoming data are cleared
+    -- 
+    -- The data are repacked to 64bit first to speed up data transfer from the FIFOs to the 10GbE port
+    -- The pipeline_ready module is needed to alleviate timing errors
+    -----------------------------------------------------------------------------
+
+    p_overide_empty : PROCESS(dp_counter_data_src_out_arr(tabno))
+    BEGIN
+      dp_repack_snk_in_arr(tabno)       <= dp_counter_data_src_out_arr(tabno);
+      dp_repack_snk_in_arr(tabno).sop   <= dp_counter_count_src_out_arr(0).sop;
+      dp_repack_snk_in_arr(tabno).eop   <= dp_counter_count_src_out_arr(0).eop;
+      dp_repack_snk_in_arr(tabno).empty <= (OTHERS => '0');
+    END PROCESS;
+
+    u_dp_repack_data : ENTITY dp_lib.dp_repack_data
+    GENERIC MAP (
+      g_in_dat_w      => c_indata_w,  -- 32
+      g_in_nof_words  => 2,
+      g_in_symbol_w   => 8,
+      g_out_dat_w     => c_data_w,    -- 64
+      g_out_nof_words => 1,
+      g_out_symbol_w  => 8
+    )
+    PORT MAP (
+      clk            => dp_clk,
+      rst            => dp_rst,
+
+      snk_in         => dp_repack_snk_in_arr(tabno),
+                   
+      src_out        => dp_fifo_sc_snk_in_arr(tabno),
+      src_in         => c_dp_siso_rdy
+    );
+
+    u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+    GENERIC MAP (
+      g_data_w         => c_data_w,
+      g_empty_w        => c_empty_w,
+      g_use_empty      => TRUE,
+      g_use_ctrl       => TRUE,
+      g_use_bsn        => FALSE,
+      g_use_channel    => FALSE,
+      g_fifo_size      => c_dp_fifo_sc_size
+   )
+    PORT MAP (
+      rst         => dp_rst,
+      clk         => dp_clk,
+  
+      snk_in      => dp_fifo_sc_snk_in_arr(tabno),
+  
+      src_in      => dp_fifo_sc_src_in_arr(tabno),
+      src_out     => dp_fifo_sc_src_out_arr(tabno)
+    );
+
+    u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+    PORT MAP(
+      rst         => dp_rst,
+      clk         => dp_clk,
+  
+      snk_in      => dp_fifo_sc_src_out_arr(tabno),
+      snk_out     => dp_fifo_sc_src_in_arr(tabno),
+  
+      src_in      => dp_pipeline_ready_src_in_arr(tabno),
+      src_out     => dp_pipeline_ready_src_out_arr(tabno)
+    );
+
+  END GENERATE;
+
+  -----------------------------------------------------------------------------
+  -- dp_mux the g_nof_tabs streams into a single stream
+  -----------------------------------------------------------------------------
+  u_mux : ENTITY dp_lib.dp_mux
+  GENERIC MAP (
+    g_data_w          => c_data_w,
+    g_empty_w        => c_empty_w,
+    g_use_empty      => TRUE,
+    g_error_w         => 1,
+    g_mode            => 1, -- forced round robin mode
+    g_nof_input       => g_nof_tabs,
+    g_fifo_size       => array_init(1024, g_nof_tabs),  -- FIFO is not used, but generic must match g_nof_input
+    g_fifo_fill       => array_init(0, g_nof_tabs)   -- FIFO is not used, but generic must match g_nof_input
+  )
+  PORT MAP (
+    rst         => dp_rst,
+    clk         => dp_clk,
+    -- ST sinks
+    snk_out_arr => dp_pipeline_ready_src_in_arr,   -- OUT = request to upstream ST source
+    snk_in_arr  => dp_pipeline_ready_src_out_arr,
+    -- ST source
+    src_in      => dp_mux_src_in,  -- IN  = request from downstream ST sink
+    src_out     => src_out
+  );
+
+  -----------------------------------------------------------------------------
+  -- Enable fifo readout
+  -----------------------------------------------------------------------------
+  dp_mux_src_in.ready <= src_in.ready and end_of_packet_latched and not dp_fifo_sc_src_out_arr(c_nof_fifos-1).eop;
+  dp_mux_src_in.xon   <= src_in.xon ;
+
+
+  -----------------------------------------------------------------------------
+  -- Generate signal to enable readout of the fifos 
+  -----------------------------------------------------------------------------
+  end_of_packet <= dp_counter_count_src_out_arr(0).eop;
+
+  p_dp_mux_ctrl : PROCESS (dp_rst, dp_clk)
+  BEGIN
+    IF dp_rst = '1' THEN
+      end_of_packet_latched <= '0';
+    ELSE
+      IF rising_edge(dp_clk) THEN
+        IF end_of_packet = '1' THEN
+          end_of_packet_latched <= '1';
+        ELSIF dp_fifo_sc_src_out_arr(c_nof_fifos-1).eop = '1' THEN
+          end_of_packet_latched <= '0';
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+
+END str;

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_reorder.vhd

--------------------------------------------------------------------------------
---
--- Copyright (C) 2017
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Author:
--- . Daniel van der Schuur
--- Purpose:
--- . TAB<->CB transpose stage
--- Description:
--- . Input : 12 TAB streams carrying 5CB each
--- . Output:  5 CB  streams carrying 12TABs each
-
-LIBRARY IEEE, common_lib, work, technology_lib, mm_lib, unb1_board_lib, dp_lib, tech_tse_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE common_lib.common_str_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
-USE unb1_board_lib.unb1_board_pkg.ALL;
-USE tech_tse_lib.tech_tse_pkg.ALL;
-USE technology_lib.technology_select_pkg.ALL;
-
-ENTITY arts_unb1_sc4_output_iquv_reorder IS
-  GENERIC (
-    g_nof_tabs             : NATURAL; --12 TABs
-    g_nof_compound_beams   : NATURAL; --5 CB
-    g_nof_stokes           : NATURAL; --1 for stokes I, 4 for stokes IQUV
-    g_nof_bytes_per_packet : NATURAL; --6250 for stokes I, 8000 for stokes IQUV
-    g_nof_channels         : NATURAL
-  ); 
-  PORT (
-    dp_rst               : IN  STD_LOGIC;
-    dp_clk               : IN  STD_LOGIC;  
-
-    snk_in_arr           : IN  t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); -- NOTE: All streams must be in sync
-
-    src_out_arr          : OUT t_dp_sosi_arr(g_nof_compound_beams-1 DOWNTO 0)
-  );
-END arts_unb1_sc4_output_iquv_reorder;
-
-
-ARCHITECTURE str OF arts_unb1_sc4_output_iquv_reorder IS
-
-  CONSTANT c_data_w               : NATURAL := g_nof_stokes*c_byte_w;
-  CONSTANT c_nof_words_per_packet : NATURAL := g_nof_bytes_per_packet/(c_data_w/c_byte_w);
-  CONSTANT c_dp_fifo_sc_size      : NATURAL := c_nof_words_per_packet*12;
-  CONSTANT c_dp_channel_w         : NATURAL := 4*c_byte_w; --4 bytes: TAB, CB, Subband, Channel index.
-
-  SIGNAL dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0);
-
-  SIGNAL dp_fifo_sc_src_out_arr   : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_fifo_sc_src_in_arr    : t_dp_siso_arr(g_nof_tabs-1 DOWNTO 0);
-
-  SIGNAL dp_mux_snk_in_arr        : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_mux_snk_out_arr       : t_dp_siso_arr(g_nof_tabs-1 DOWNTO 0);
-
-  SIGNAL dp_mux_src_out           : t_dp_sosi;
-   
-BEGIN
-
-  -----------------------------------------------------------------------------
-  -- Re-assign frame boundaries (SOP, EOP) based on g_nof_bytes_per_packet
-  -- . Note: behind the FIFOs would have been be better as we wouldn't need to
-  --   pass SOP,EOP through the FIFOs. But dp_block_gen does not have flow 
-  --   control. We want to preserve flow control from the packetizing stage all
-  --   the way to below FIFOs to prevent having to use even more M9Ks downstream.
-  -----------------------------------------------------------------------------
-  gen_dp_block_gen : FOR i IN 0 TO g_nof_tabs-1 GENERATE
-    u_dp_block_gen : ENTITY dp_lib.dp_block_gen
-    GENERIC MAP (
-      g_use_src_in       => FALSE,
-      g_nof_data         => c_nof_words_per_packet*g_nof_channels,
-      g_preserve_sync    => TRUE,
-      g_preserve_bsn     => TRUE,
-      g_preserve_channel => TRUE
-    )
-    PORT MAP(
-      clk        => dp_clk,
-      rst        => dp_rst,
-     
-      snk_in     => snk_in_arr(i),
-      src_out    => dp_block_gen_src_out_arr(i)
-    );    
-  END GENERATE;
-
-  -----------------------------------------------------------------------------
-  -- IQUV: Buffer the 12 TAB streams
-  -- . The 12 TAB streams are output in sync. We need to buffer them here so
-  --   dp_mux has the time to multiplex them.
-  -----------------------------------------------------------------------------
-  gen_dp_fifo_sc : FOR i IN 0 TO g_nof_tabs-1 GENERATE
-
-    u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
-    GENERIC MAP (
-      g_data_w         => c_data_w,
-      g_use_ctrl       => TRUE, 
-      g_use_sync       => sel_a_b(i=0, TRUE, FALSE), -- Pass on sync of stream 0.
-      g_use_channel    => TRUE,
-      g_channel_w      => c_dp_channel_w,
-      g_use_complex    => FALSE,
-      g_fifo_size      => c_dp_fifo_sc_size, --FIXME FIFO 0 does not need to be as deep as FIFO 11
-      g_fifo_af_margin => 0
-    )
-    PORT MAP (
-      rst         => dp_rst,
-      clk         => dp_clk,
-
-      snk_in      => dp_block_gen_src_out_arr(i),
-      src_in      => dp_fifo_sc_src_in_arr(i),
-      src_out     => dp_fifo_sc_src_out_arr(i)
-    );
-  END GENERATE;
- 
-  -----------------------------------------------------------------------------
-  -- IQUV: Multiplex the 12 TAB streams onto 1 stream
-  -----------------------------------------------------------------------------
-  dp_mux_snk_in_arr <= func_dp_stream_arr_reverse_range(dp_fifo_sc_src_out_arr);
-  dp_fifo_sc_src_in_arr <= func_dp_stream_arr_reverse_range(dp_mux_snk_out_arr);
-
-  u_dp_mux : ENTITY dp_lib.dp_mux
-  GENERIC MAP (
-    g_data_w            => c_data_w,
-    g_use_sync          => TRUE,
-    g_mode              => 1, -- Fixed input order determined by SOP,EOP.
-    g_nof_input         => g_nof_tabs,
-    g_append_channel_lo => FALSE, -- Don't mess with our channel field
-    g_in_channel_w      => c_dp_channel_w,
-    g_use_in_channel    => TRUE,
-    g_use_fifo          => FALSE,
-    g_fifo_size         => array_init(0, g_nof_tabs), --unused but required
-    g_fifo_fill         => array_init(0, g_nof_tabs) --unused but required
-  )
-  PORT MAP (
-    clk         => dp_clk,
-    rst         => dp_rst,
-
-    snk_in_arr  => dp_mux_snk_in_arr,
-    snk_out_arr => dp_mux_snk_out_arr,
-
-    src_out     => dp_mux_src_out,
-    src_in      => c_dp_siso_rdy
-  );  
-
-  -----------------------------------------------------------------------------
-  -- IQUV: Demultiplex the 5 beams from the stream:
-  -- . The input stream carries 500 timesample (2000 words) packets for TAB 0..11
-  -- . After 50*12 packets (25000 timesamples of 12 TABS), we get the next subband
-  -- . After 24 subbands, we get the next beam which should be switched to a new demux output
-  --   . Use the channel field to switch dp_demux output
-  -----------------------------------------------------------------------------
-  u_dp_demux : ENTITY dp_lib.dp_demux
-  GENERIC MAP (
-    g_mode              => 2, --Use sel_ctrl
-    g_nof_output        => g_nof_compound_beams,
-    g_sel_ctrl_invert   => TRUE,
-    g_remove_channel_lo => FALSE 
-  )
-  PORT MAP (
-    clk         => dp_clk,
-    rst         => dp_rst,
-
-    sel_ctrl    => TO_UINT(dp_mux_src_out.channel(18 DOWNTO 16)), -- Byte that contains the 3 bits needed to encode beam index 0..4
-
-    snk_in      => dp_mux_src_out, -- Single stream carrying 500t of TAB0, 500t of TAB1, .. 500t of TAB11
-
-    src_out_arr => src_out_arr
-  );
- 
-END str;

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_processing.vhd

@@ -43,6 +43,7 @@ LIBRARY wpfb_lib, filter_lib, rTwoSDF_lib;
     USE wpfb_lib.wpfb_pkg.ALL;
     USE filter_lib.fil_pkg.ALL;
     USE rTwoSDF_lib.rTwoSDFPkg.ALL;
+LIBRARY arts_tab_beamformer_lib;
 
 
 ENTITY arts_unb1_sc4_processing IS --FIXME Given the generics, this could be used for SC3 as well (8 dishes, less TABs). Rename/move required?
@@ -195,7 +196,7 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS
   CONSTANT c_output_11tab_1iab  : NATURAL := 0; -- The intermediate production mode
   CONSTANT c_output_tab_iquv    : NATURAL := 1; -- The ultimate production mode
   CONSTANT c_output_iquv_iab_all: NATURAL := 2; -- First test mode
-  CONSTANT c_output_select      : NATURAL := c_output_iquv_iab_all;  -- Make your choice here
+  CONSTANT c_output_select      : NATURAL := c_output_tab_iquv;  -- Make your choice here
 
   -- signals to generate an artificial sync during simulation
   SIGNAL fake_sync_enable : STD_LOGIC := '1';
@@ -342,6 +343,27 @@ BEGIN
   -------------------------------------------------------------------------------
   -- TAB Beam former FIFO stage: BF module requires flow control
   -------------------------------------------------------------------------------
+  u_arts_tab_beamformer : ENTITY arts_tab_beamformer_lib.arts_tab_beamformer
+  GENERIC MAP (
+    g_nof_inputs   => g_nof_telescopes,
+    g_nof_tabs     => g_nof_tabs,
+    g_nof_beamlets => 88,
+    g_data_w       => c_wpfb_out_dat_w
+  )
+  PORT MAP (
+    dp_clk      => dp_clk,
+    dp_rst      => dp_rst,
+
+    mm_clk      => mm_clk,
+    mm_rst      => mm_rst,
+
+    ram_mosi    => ram_bf_weights_mosi,
+    ram_miso    => ram_bf_weights_miso,
+
+    snk_in_arr  => wpfb_src_out_arr,
+    src_out_arr => bf_raw_src_out_arr
+  );
+
 --  gen_dp_fifo_sc : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
 --    u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
 --    GENERIC MAP(
@@ -398,35 +420,35 @@ BEGIN
 --    out_qua_sosi_arr    => bf_qua_src_out_arr
 --  );     
 --
---  -------------------------------------------------------------------------------
---  -- IQUV calculation of TABs
---  -------------------------------------------------------------------------------
---
---  gen_iquv : FOR i IN 0 TO g_nof_tabs-1 GENERATE
---    u_iquv : ENTITY iquv_lib.iquv
---    GENERIC MAP (
---      g_sim              => g_sim,
---      g_use_accum        => c_use_accum_iquv,
---      g_nof_int          => c_nof_int_iquv,
---      g_in_data_w        => c_in_data_w_iquv,
---      g_out_data_w       => c_out_data_w_iquv
---    )
---    PORT MAP (
---      dp_rst     => dp_rst,
---      dp_clk     => dp_clk,
---      in_complex => bf_raw_src_out_arr(i),
---      i_out      => iquv_i_out_arr(i),
---      q_out      => iquv_q_out_arr(i),
---      u_out      => iquv_u_out_arr(i),
---      v_out      => iquv_v_out_arr(i)
---    );
---
---    iquv_src_out_arr(i).valid <= iquv_iab_i_out.valid;
---    iquv_src_out_arr(i).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
---                                                              & iquv_u_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
---                                                              & iquv_q_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
---                                                              & iquv_i_out_arr(i).data(c_out_data_w_iquv-1 downto 0);
---  END GENERATE;
+  -------------------------------------------------------------------------------
+  -- IQUV calculation of TABs
+  -------------------------------------------------------------------------------
+
+  gen_iquv : FOR i IN 0 TO g_nof_tabs-1 GENERATE
+    u_iquv : ENTITY iquv_lib.iquv
+    GENERIC MAP (
+      g_sim              => g_sim,
+      g_use_accum        => c_use_accum_iquv,
+      g_nof_int          => c_nof_int_iquv,
+      g_in_data_w        => c_in_data_w_iquv,
+      g_out_data_w       => c_out_data_w_iquv
+    )
+    PORT MAP (
+      dp_rst     => dp_rst,
+      dp_clk     => dp_clk,
+      in_complex => bf_raw_src_out_arr(i),
+      i_out      => iquv_i_out_arr(i),
+      q_out      => iquv_q_out_arr(i),
+      u_out      => iquv_u_out_arr(i),
+      v_out      => iquv_v_out_arr(i)
+    );
+
+    iquv_src_out_arr(i).valid <= iquv_iab_i_out.valid;
+    iquv_src_out_arr(i).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
+                                                              & iquv_u_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
+                                                              & iquv_q_out_arr(i).data(c_out_data_w_iquv-1 downto 0)
+                                                              & iquv_i_out_arr(i).data(c_out_data_w_iquv-1 downto 0);
+  END GENERATE;