-Set BG block boundaries to 176 while using a RAM range of 128 words;

-Also set BG gap size to 256-176.

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd

@@ -126,8 +126,9 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
   SIGNAL pout_wdi                   : STD_LOGIC;
 
   -- Block generator
-  CONSTANT c_bg_block_size          : NATURAL := 2*64; -- 2 interleaved streams
-  CONSTANT c_bg_gapsize             : NATURAL := 0;
+  CONSTANT c_bg_block_size          : NATURAL := 176;    -- Note: our block boundaries (176) are different from the functional block size (128)
+  CONSTANT c_bg_mem_high_addr       : NATURAL := 2*64-1; -- 2 interleaved streams.
+  CONSTANT c_bg_gapsize             : NATURAL := 256-176;
   CONSTANT c_bg_blocks_per_sync     : NATURAL := 781250;
   CONSTANT c_bg_ctrl                : t_diag_block_gen := (sel_a_b(g_sim, '1', '0'), -- enable: On by default in simulation; MM enable required on hardware.
                                                            sel_a_b(g_sim, '1', '0'), -- enable_sync        
@@ -135,7 +136,7 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
                                                           TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
                                                           TO_UVEC(        c_bg_gapsize, c_diag_bg_gapsize_w),
                                                           TO_UVEC(                   0, c_diag_bg_mem_low_adrs_w),
-                                                          TO_UVEC(   c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
+                                                          TO_UVEC(c_bg_mem_high_addr-1, c_diag_bg_mem_high_adrs_w),
                                                           TO_UVEC(                   0, c_diag_bg_bsn_init_w));
   -- Interface: 10GbE
   CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
@@ -173,10 +174,10 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
   SIGNAL reg_ppsh_mosi              : t_mem_mosi;  
   SIGNAL reg_ppsh_miso              : t_mem_miso;  
   -- Block gens                                    
-  SIGNAL reg_diag_bg_mosi              : t_mem_mosi;  
-  SIGNAL reg_diag_bg_miso              : t_mem_miso;  
-  SIGNAL ram_diag_bg_mosi              : t_mem_mosi;  
-  SIGNAL ram_diag_bg_miso              : t_mem_miso;
+  SIGNAL reg_diag_bg_mosi           : t_mem_mosi;  
+  SIGNAL reg_diag_bg_miso           : t_mem_miso;  
+  SIGNAL ram_diag_bg_mosi           : t_mem_mosi;  
+  SIGNAL ram_diag_bg_miso           : t_mem_miso;
   -- . eth1g
   SIGNAL eth1g_tse_clk              : STD_LOGIC;
   SIGNAL eth1g_mm_rst               : STD_LOGIC;
@@ -188,12 +189,12 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
   SIGNAL eth1g_ram_mosi             : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL eth1g_ram_miso             : t_mem_miso;           
   -- . 10GbE offload
-  SIGNAL reg_tr_10GbE_mosi              : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_miso              : t_mem_miso := c_mem_miso_rst;
-  SIGNAL reg_tr_xaui_mosi               : t_mem_mosi;
-  SIGNAL reg_tr_xaui_miso               : t_mem_miso := c_mem_miso_rst;
-  SIGNAL reg_mdio_mosi_arr              : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-  SIGNAL reg_mdio_miso_arr              : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);     
+  SIGNAL reg_tr_10GbE_mosi          : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_miso          : t_mem_miso := c_mem_miso_rst;
+  SIGNAL reg_tr_xaui_mosi           : t_mem_mosi;
+  SIGNAL reg_tr_xaui_miso           : t_mem_miso := c_mem_miso_rst;
+  SIGNAL reg_mdio_mosi_arr          : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+  SIGNAL reg_mdio_miso_arr          : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);     
 
 BEGIN
 
@@ -357,16 +358,16 @@ BEGIN
     g_sim_node_nr => g_sim_node_nr
   )
   PORT MAP (
-    xo_clk         => xo_clk,
-    xo_rst_n       => xo_rst_n,                    
-    xo_rst         => xo_rst,                      
+    xo_clk                     => xo_clk,
+    xo_rst_n                   => xo_rst_n,                    
+    xo_rst                     => xo_rst,                      
 
-    mm_rst         => mm_rst,                      
-    mm_clk         => mm_clk,                      
-    mm_locked      => mm_locked,                   
-    cal_clk        => cal_rec_clk,                     
+    mm_rst                     => mm_rst,                      
+    mm_clk                     => mm_clk,                      
+    mm_locked                  => mm_locked,                   
+    cal_clk                    => cal_rec_clk,                     
 
-    pout_wdi       => pout_wdi,                    
+    pout_wdi                   => pout_wdi,                    
     
     -- Manual WDI override
     reg_wdi_mosi               => reg_wdi_mosi,                  
@@ -393,25 +394,25 @@ BEGIN
     reg_diag_bg_mosi           => reg_diag_bg_mosi,                 
     reg_diag_bg_miso           => reg_diag_bg_miso,                 
 
-    reg_tr_10GbE_mosi              => reg_tr_10GbE_mosi,              
-    reg_tr_10GbE_miso              => reg_tr_10GbE_miso,              
+    reg_tr_10GbE_mosi          => reg_tr_10GbE_mosi,              
+    reg_tr_10GbE_miso          => reg_tr_10GbE_miso,              
 
-    reg_mdio_mosi_arr              => reg_mdio_mosi_arr,              
-    reg_mdio_miso_arr              => reg_mdio_miso_arr,              
+    reg_mdio_mosi_arr          => reg_mdio_mosi_arr,              
+    reg_mdio_miso_arr          => reg_mdio_miso_arr,              
 
-    reg_tr_xaui_mosi               => reg_tr_xaui_mosi,               
-    reg_tr_xaui_miso               => reg_tr_xaui_miso,    
+    reg_tr_xaui_mosi           => reg_tr_xaui_mosi,               
+    reg_tr_xaui_miso           => reg_tr_xaui_miso,    
      
     -- eth1g     
-    eth1g_tse_clk                  => eth1g_tse_clk,                  
-    eth1g_mm_rst                   => eth1g_mm_rst,                   
-    eth1g_tse_mosi                 => eth1g_tse_mosi,                 
-    eth1g_tse_miso                 => eth1g_tse_miso,                 
-    eth1g_reg_mosi                 => eth1g_reg_mosi,                 
-    eth1g_reg_miso                 => eth1g_reg_miso,                 
-    eth1g_reg_interrupt            => eth1g_reg_interrupt,
-    eth1g_ram_mosi                 => eth1g_ram_mosi,                 
-    eth1g_ram_miso                 => eth1g_ram_miso                 
+    eth1g_tse_clk              => eth1g_tse_clk,                  
+    eth1g_mm_rst               => eth1g_mm_rst,                   
+    eth1g_tse_mosi             => eth1g_tse_mosi,                 
+    eth1g_tse_miso             => eth1g_tse_miso,                 
+    eth1g_reg_mosi             => eth1g_reg_mosi,                 
+    eth1g_reg_miso             => eth1g_reg_miso,                 
+    eth1g_reg_interrupt        => eth1g_reg_interrupt,
+    eth1g_ram_mosi             => eth1g_ram_mosi,                 
+    eth1g_ram_miso             => eth1g_ram_miso                 
   );
 
   -----------------------------------------------------------------------------