Ported tb_unb1_bn_capture_input.vhd from...

Ported tb_unb1_bn_capture_input.vhd from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk and added it to the regression test.

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

@@ -11,8 +11,9 @@ synth_files =
     src/vhdl/unb1_bn_capture.vhd
     
 test_bench_files =   
-    tb/vhdl/tb_unb1_bn_capture.vhd
+    tb/vhdl/tb_unb1_bn_capture_input.vhd
     tb/vhdl/tb_node_unb1_bn_capture.vhd
+    #tb/vhdl/tb_unb1_bn_capture.vhd
 
 
 [modelsim_project_file]