initial commit of ported Block RAM

libraries/technology/ip_ultrascale/ram/README.txt

+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
+
+Contents:
+
+1) RAM components
+2) ROM components
+3) Arria10 IP
+4) Inferred IP
+5) Memory initialisation file
+6) Implementation options (LUTs or block RAM)
+7) Synthesis trials
+
+
+1) RAM components:
+
+  ip_arria10_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths
+  ip_arria10_ram_crw_crw  = Two read/write ports each port with own port clock and with same address and data width on both ports
+  ip_arria10_ram_cr_cw    = One read port with clock and one write port with clock and with same address and data width on both ports
+  ip_arria10_ram_r_w      = Single clock, one read port and one write port and with same address and data width on both ports
+  
+
+2) ROM components:
+  ip_arria10_rom_r_w      = Not available and not needed, because the ip_arria10_ram_r_w can be used for ROM IP by not connecting the
+                            write port.
+
+
+3) Arria10 IP
+
+  The IP only needs to be generated with
+  
+   ./generate_ip.sh
+   
+  if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
+  
+  The instantiation is copied manually from the ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+  
+  It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package, 
+  that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
+
+
+4) Inferred IP
+
+  The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+  The ram_crwk_crw can not be inferred.
+  For the other RAM the g_inferred generic is set to FALSE because the inferred instances do not yet support g_init_file.
+  It is possible to init the RAM using a function e.g.:
+ 
+      function init_ram
+        return memory_t is 
+        variable tmp : memory_t := (others => (others => '0'));
+      begin 
+        for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop 
+          -- Initialize each address with the address itself
+          tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
+        end loop;
+        return tmp;
+      end init_ram;  
+    
+      -- Declare the RAM signal and specify a default value.  Quartus II
+      -- will create a memory initialization file (.mif) based on the 
+      -- default value.
+      signal ram : memory_t := init_ram;
+
+5) Memory initialisation file
+
+  To support the g_init_file requires first reading the file in a certain format. For us an integer format or SLV format
+  with one value per line (line number = address) would be fine. Using SLV format is necessary if the RAM data is wider
+  than 32 bit, because VHDL integer range is only 2**32. The tb_common_pkg has functiosn to read such a file. Quartus
+  creates a mif file from this when it infers the RAM. However our current UniBoard1 designs provide a mif file that fits
+  the RAM IP. Therefore it is easier initially to also use the RAM IP for Arria10. In future for RadioHDL a generic
+  RAM init file format is preferrable though.
+ 
+
+6) Implementation options (LUTs or block RAM)
+
+  The IP and inferred RAM can be set to use LUTs (MLAB) or block RAM (M20K), however this is not supported yet.
+  
+  . For IP RAM this would imply adding a generic to set the appropriate parameter in the altera_syncram
+  . For inferred RAM is would imply adding a generic to be used for the syntype attribute. 
+    From http://www.alterawiki.com/wiki/Mapping_SRLs_to_registers,_MLABs,_or_Block_RAMs:  
+
+      entity
+          g_ramstyle : STRING := "MLAB,no_rw_check"
+      architecture  
+          attribute ramstyle : string;
+    
+          signal ram : memory_t := init_ram;
+          attribute ramstyle of ram : signal is g_ramstyle; 
+  
+
+7) Synthesis trials
+
+  The quartus/ram.qpf Quartus project was used to verify that the inferred RAM and the block RAM IP actually synthesise
+  to the appropriate FPGA resources.
+  Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+  in the file tab of the Quartus project navigator window.
+  Then check the resource usage in the synthesis and fitter reports.

libraries/technology/ip_ultrascale/ram/hdllib.cfg

+hdl_lib_name = ip_ultrascale_ram
+hdl_library_clause_name = ip_ultrascale_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_ultrascale
+
+synth_files =
+    ip_ultrascale_true_dual_port_ram_dual_clock.vhd
+#    ip_ultrascale_simple_dual_port_ram_dual_clock.vhd
+#    ip_ultrascale_simple_dual_port_ram_single_clock.vhd
+    
+#    ip_ultrascale_ram_crwk_crw.vhd
+    ip_ultrascale_ram_crw_crw.vhd
+#    ip_ultrascale_ram_cr_cw.vhd
+#    ip_ultrascale_ram_r_w.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_cr_cw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclk     : IN  STD_LOGIC ;
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclk     : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END ip_arria10_e2sg_ram_cr_cw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
+
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+  COMPONENT altera_syncram
+  GENERIC (
+          address_aclr_b  : string;
+          address_reg_b  : string;
+          clock_enable_input_a  : string;
+          clock_enable_input_b  : string;
+          clock_enable_output_b  : string;
+          init_file  : string;
+          intended_device_family  : string;
+          lpm_type  : string;
+          numwords_a  : integer;
+          numwords_b  : integer;
+          operation_mode  : string;
+          outdata_aclr_b  : string;
+          outdata_reg_b  : string;
+          power_up_uninitialized  : string;
+          read_during_write_mode_mixed_ports : string;
+          widthad_a  : integer;
+          widthad_b  : integer;
+          width_a  : integer;
+          width_b  : integer;
+          width_byteena_a  : integer
+  );
+  PORT (
+      address_a : in std_logic_vector(g_adr_w-1 downto 0);
+      address_b : in std_logic_vector(g_adr_w-1 downto 0);
+      clock0 : in std_logic;
+      clock1 : in std_logic;
+      data_a : in std_logic_vector(g_dat_w-1 downto 0);
+      wren_a : in std_logic;
+      q_b : out std_logic_vector(g_dat_w-1 downto 0)
+  );
+  END COMPONENT;
+  
+  SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+  SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+  
+  SIGNAL out_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+  SIGNAL reg_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+  
+BEGIN
+
+  ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+  
+  gen_ip : IF g_inferred=FALSE GENERATE
+    -- Copied from ip_arria10_e2sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e2sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+    u_altera_syncram : altera_syncram
+    GENERIC MAP (
+            address_aclr_b  => "NONE",
+            address_reg_b  => "CLOCK1",
+            clock_enable_input_a  => "BYPASS",
+            clock_enable_input_b  => "BYPASS",
+            clock_enable_output_b  => "BYPASS",
+            init_file  => g_init_file,
+            intended_device_family  => "Arria 10",
+            lpm_type  => "altera_syncram",
+            numwords_a  => g_nof_words,
+            numwords_b  => g_nof_words,
+            operation_mode  => "DUAL_PORT",
+            outdata_aclr_b  => "NONE",
+            outdata_reg_b  => c_outdata_reg_b,
+            power_up_uninitialized  => "FALSE",
+            read_during_write_mode_mixed_ports => "OLD_DATA",
+            widthad_a  => g_adr_w,
+            widthad_b  => g_adr_w,
+            width_a  => g_dat_w,
+            width_b  => g_dat_w,
+            width_byteena_a  => 1
+    )
+    PORT MAP (
+        address_a => wraddress,
+        address_b => rdaddress,
+        clock0 => wrclk,
+        clock1 => rdclk,
+        data_a => data,
+        wren_a => wren,
+        q_b => q
+    );
+  END GENERATE;
+  
+  gen_inferred : IF g_inferred=TRUE GENERATE
+    rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+    wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+    
+    u_mem : entity work.ip_arria10_e2sg_simple_dual_port_ram_dual_clock
+    generic map (
+      DATA_WIDTH => g_dat_w,
+      ADDR_WIDTH => g_adr_w
+    )
+    port map (
+      rclk  => rdclk,
+      wclk  => wrclk,
+      raddr => rdaddr,
+      waddr => wraddr,
+      data  => data,
+      we    => wren,
+      q     => out_q
+    );
+  
+    reg_q <= out_q WHEN rising_edge(rdclk);
+    
+    q <= out_q WHEN g_rd_latency=1 ELSE reg_q;  
+  END GENERATE;
+  
+END SYN;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+ENTITY ip_ultrascale_ram_crw_crw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clk_a     : IN STD_LOGIC  := '1';
+    clk_b     : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END ip_ultrascale_ram_crw_crw;
+
+
+ARCHITECTURE ip_ultrascale_ram_crw_crw_arch OF ip_ultrascale_ram_crw_crw IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF ip_ultrascale_ram_crw_crw_arch: ARCHITECTURE IS "yes";
+  COMPONENT blk_mem_gen_v8_4_5 IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_XDEVICEFAMILY : STRING;
+      C_ELABORATION_DIR : STRING;
+      C_INTERFACE_TYPE : INTEGER;
+      C_AXI_TYPE : INTEGER;
+      C_AXI_SLAVE_TYPE : INTEGER;
+      C_USE_BRAM_BLOCK : INTEGER;
+      C_ENABLE_32BIT_ADDRESS : INTEGER;
+      C_CTRL_ECC_ALGO : STRING;
+      C_HAS_AXI_ID : INTEGER;
+      C_AXI_ID_WIDTH : INTEGER;
+      C_MEM_TYPE : INTEGER;
+      C_BYTE_SIZE : INTEGER;
+      C_ALGORITHM : INTEGER;
+      C_PRIM_TYPE : INTEGER;
+      C_LOAD_INIT_FILE : INTEGER;
+      C_INIT_FILE_NAME : STRING;
+      C_INIT_FILE : STRING;
+      C_USE_DEFAULT_DATA : INTEGER;
+      C_DEFAULT_DATA : STRING;
+      C_HAS_RSTA : INTEGER;
+      C_RST_PRIORITY_A : STRING;
+      C_RSTRAM_A : INTEGER;
+      C_INITA_VAL : STRING;
+      C_HAS_ENA : INTEGER;
+      C_HAS_REGCEA : INTEGER;
+      C_USE_BYTE_WEA : INTEGER;
+      C_WEA_WIDTH : INTEGER;
+      C_WRITE_MODE_A : STRING;
+      C_WRITE_WIDTH_A : INTEGER;
+      C_READ_WIDTH_A : INTEGER;
+      C_WRITE_DEPTH_A : INTEGER;
+      C_READ_DEPTH_A : INTEGER;
+      C_ADDRA_WIDTH : INTEGER;
+      C_HAS_RSTB : INTEGER;
+      C_RST_PRIORITY_B : STRING;
+      C_RSTRAM_B : INTEGER;
+      C_INITB_VAL : STRING;
+      C_HAS_ENB : INTEGER;
+      C_HAS_REGCEB : INTEGER;
+      C_USE_BYTE_WEB : INTEGER;
+      C_WEB_WIDTH : INTEGER;
+      C_WRITE_MODE_B : STRING;
+      C_WRITE_WIDTH_B : INTEGER;
+      C_READ_WIDTH_B : INTEGER;
+      C_WRITE_DEPTH_B : INTEGER;
+      C_READ_DEPTH_B : INTEGER;
+      C_ADDRB_WIDTH : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
+      C_MUX_PIPELINE_STAGES : INTEGER;
+      C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
+      C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
+      C_USE_SOFTECC : INTEGER;
+      C_USE_ECC : INTEGER;
+      C_EN_ECC_PIPE : INTEGER;
+      C_READ_LATENCY_A : INTEGER;
+      C_READ_LATENCY_B : INTEGER;
+      C_HAS_INJECTERR : INTEGER;
+      C_SIM_COLLISION_CHECK : STRING;
+      C_COMMON_CLK : INTEGER;
+      C_DISABLE_WARN_BHV_COLL : INTEGER;
+      C_EN_SLEEP_PIN : INTEGER;
+      C_USE_URAM : INTEGER;
+      C_EN_RDADDRA_CHG : INTEGER;
+      C_EN_RDADDRB_CHG : INTEGER;
+      C_EN_DEEPSLEEP_PIN : INTEGER;
+      C_EN_SHUTDOWN_PIN : INTEGER;
+      C_EN_SAFETY_CKT : INTEGER;
+      C_DISABLE_WARN_BHV_RANGE : INTEGER;
+      C_COUNT_36K_BRAM : STRING;
+      C_COUNT_18K_BRAM : STRING;
+      C_EST_POWER_SUMMARY : STRING
+    );
+    PORT (
+      clka : IN STD_LOGIC;
+      rsta : IN STD_LOGIC;
+      ena : IN STD_LOGIC;
+      regcea : IN STD_LOGIC;
+      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+      dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      clkb : IN STD_LOGIC;
+      rstb : IN STD_LOGIC;
+      enb : IN STD_LOGIC;
+      regceb : IN STD_LOGIC;
+      web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+      dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      injectsbiterr : IN STD_LOGIC;
+      injectdbiterr : IN STD_LOGIC;
+      eccpipece : IN STD_LOGIC;
+      sbiterr : OUT STD_LOGIC;
+      dbiterr : OUT STD_LOGIC;
+      rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sleep : IN STD_LOGIC;
+      deepsleep : IN STD_LOGIC;
+      shutdown : IN STD_LOGIC;
+      rsta_busy : OUT STD_LOGIC;
+      rstb_busy : OUT STD_LOGIC;
+      s_aclk : IN STD_LOGIC;
+      s_aresetn : IN STD_LOGIC;
+      s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_wlast : IN STD_LOGIC;
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rlast : OUT STD_LOGIC;
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi_injectsbiterr : IN STD_LOGIC;
+      s_axi_injectdbiterr : IN STD_LOGIC;
+      s_axi_sbiterr : OUT STD_LOGIC;
+      s_axi_dbiterr : OUT STD_LOGIC;
+      s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+    );
+  END COMPONENT blk_mem_gen_v8_4_5;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF ip_ultrascale_ram_crw_crw_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_5,Vivado 2022.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF ip_ultrascale_ram_crw_crw_arch : ARCHITECTURE IS "ip_ultrascale_ram_crw_crw,blk_mem_gen_v8_4_5,{}";
+  
+BEGIN
+
+  ASSERT g_rd_latency=1   REPORT "ip_ultrascale_ram_crw_crw : read latency must be 1 (default)" SEVERITY FAILURE;
+  ASSERT g_inferred=FALSE REPORT "ip_ultrascale_ram_crw_crw : cannot infer RAM" SEVERITY FAILURE;
+  
+  U0 : blk_mem_gen_v8_4_5
+    GENERIC MAP (
+      C_FAMILY => "virtexuplusHBM",
+      C_XDEVICEFAMILY => "virtexuplusHBM",
+      C_ELABORATION_DIR => "./",
+      C_INTERFACE_TYPE => 0,
+      C_AXI_TYPE => 1,
+      C_AXI_SLAVE_TYPE => 0,
+      C_USE_BRAM_BLOCK => 0,
+      C_ENABLE_32BIT_ADDRESS => 0,
+      C_CTRL_ECC_ALGO => "NONE",
+      C_HAS_AXI_ID => 0,
+      C_AXI_ID_WIDTH => 4,
+      C_MEM_TYPE => 2,
+      C_BYTE_SIZE => 9,
+      C_ALGORITHM => 1,
+      C_PRIM_TYPE => 1,
+      C_LOAD_INIT_FILE => 0,
+      C_INIT_FILE_NAME => "init_file",
+      C_INIT_FILE => g_init_file,
+      C_USE_DEFAULT_DATA => 0,
+      C_DEFAULT_DATA => "0",
+      C_HAS_RSTA => 0,
+      C_RST_PRIORITY_A => "CE",
+      C_RSTRAM_A => 0,
+      C_INITA_VAL => "0",
+      C_HAS_ENA => 1,
+      C_HAS_REGCEA => 0,
+      C_USE_BYTE_WEA => 0,
+      C_WEA_WIDTH => 1,
+      C_WRITE_MODE_A => "WRITE_FIRST",
+      C_WRITE_WIDTH_A => g_dat_w,
+      C_READ_WIDTH_A => g_dat_w,
+      C_WRITE_DEPTH_A => g_nof_words,
+      C_READ_DEPTH_A => g_nof_words,
+      C_ADDRA_WIDTH => g_adr_w,
+      C_HAS_RSTB => 0,
+      C_RST_PRIORITY_B => "CE",
+      C_RSTRAM_B => 0,
+      C_INITB_VAL => "0",
+      C_HAS_ENB => 1,
+      C_HAS_REGCEB => 0,
+      C_USE_BYTE_WEB => 0,
+      C_WEB_WIDTH => 1,
+      C_WRITE_MODE_B => "WRITE_FIRST",
+      C_WRITE_WIDTH_B => g_dat_w,
+      C_READ_WIDTH_B => g_dat_w,
+      C_WRITE_DEPTH_B => g_nof_words,
+      C_READ_DEPTH_B => g_nof_words,
+      C_ADDRB_WIDTH => g_adr_w,
+      C_HAS_MEM_OUTPUT_REGS_A => 1,
+      C_HAS_MEM_OUTPUT_REGS_B => 1,
+      C_HAS_MUX_OUTPUT_REGS_A => 0,
+      C_HAS_MUX_OUTPUT_REGS_B => 0,
+      C_MUX_PIPELINE_STAGES => 0,
+      C_HAS_SOFTECC_INPUT_REGS_A => 0,
+      C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
+      C_USE_SOFTECC => 0,
+      C_USE_ECC => 0,
+      C_EN_ECC_PIPE => 0,
+      C_READ_LATENCY_A => 1,
+      C_READ_LATENCY_B => 1,
+      C_HAS_INJECTERR => 0,
+      C_SIM_COLLISION_CHECK => "ALL",
+      C_COMMON_CLK => 0,
+      C_DISABLE_WARN_BHV_COLL => 0,
+      C_EN_SLEEP_PIN => 0,
+      C_USE_URAM => 0,
+      C_EN_RDADDRA_CHG => 0,
+      C_EN_RDADDRB_CHG => 0,
+      C_EN_DEEPSLEEP_PIN => 0,
+      C_EN_SHUTDOWN_PIN => 0,
+      C_EN_SAFETY_CKT => 0,
+      C_DISABLE_WARN_BHV_RANGE => 0,
+      C_COUNT_36K_BRAM => "NaN",
+      C_COUNT_18K_BRAM => "NaN",
+      C_EST_POWER_SUMMARY => "Estimated Power for IP     :     UNKNOWN"
+    )
+    PORT MAP (
+      clka => clk_a,
+      rsta => '0',
+      ena => '1',
+      regcea => '0',
+      wea(0) => wren_a,
+      addra => address_a,
+      dina => data_a,
+      douta => q_a,
+      clkb => clk_b,
+      rstb => '0',
+      enb => '1',
+      regceb => '0',
+      web(0) => wren_b,
+      addrb => address_b,
+      dinb => data_b,
+      doutb => q_b,
+      injectsbiterr => '0',
+      injectdbiterr => '0',
+      eccpipece => '0',
+      sleep => '0',
+      deepsleep => '0',
+      shutdown => '0',
+      s_aclk => '0',
+      s_aresetn => '0',
+      s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_awvalid => '0',
+      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_wlast => '0',
+      s_axi_wvalid => '0',
+      s_axi_bready => '0',
+      s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_arvalid => '0',
+      s_axi_rready => '0',
+      s_axi_injectsbiterr => '0',
+      s_axi_injectdbiterr => '0'
+    );
+
+END ip_ultrascale_ram_crw_crw_arch;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crwk_crw.vhd

+-- (C) 2001-2014 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions and other 
+-- software and tools, and its AMPP partner logic functions, and any output 
+-- files any of the foregoing (including device programming or simulation 
+-- files), and any associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License Subscription 
+-- Agreement, Altera MegaCore Function License Agreement, or other applicable 
+-- license agreement, including, without limitation, that your use is for the 
+-- sole purpose of programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_crwk_crw IS
+  GENERIC (
+    g_adr_a_w     : NATURAL := 5;
+    g_dat_a_w     : NATURAL := 32;
+    g_adr_b_w     : NATURAL := 4;
+    g_dat_b_w     : NATURAL := 64;
+    g_nof_words_a : NATURAL := 2**5;
+    g_nof_words_b : NATURAL := 2**4;
+    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
+    g_init_file   : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+    clk_a     : IN STD_LOGIC  := '1';
+    clk_b     : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+  );
+END ip_arria10_e2sg_ram_crwk_crw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crwk_crw IS
+
+  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+  COMPONENT altera_syncram
+  GENERIC (
+          address_reg_b  : string;
+          clock_enable_input_a  : string;
+          clock_enable_input_b  : string;
+          clock_enable_output_a  : string;
+          clock_enable_output_b  : string;
+          indata_reg_b  : string;
+          init_file  : string;
+          init_file_layout  : string;
+          intended_device_family  : string;
+          lpm_type  : string;
+          numwords_a  : integer;
+          numwords_b  : integer;
+          operation_mode  : string;
+          outdata_aclr_a  : string;
+          outdata_aclr_b  : string;
+          outdata_reg_a  : string;
+          outdata_reg_b  : string;
+          power_up_uninitialized  : string;
+          read_during_write_mode_port_a  : string;
+          read_during_write_mode_port_b  : string;
+          widthad_a  : integer;
+          widthad_b  : integer;
+          width_a  : integer;
+          width_b  : integer;
+          width_byteena_a  : integer;
+          width_byteena_b  : integer
+  );
+  PORT (
+      address_a : in std_logic_vector(g_adr_a_w-1 downto 0);
+      address_b : in std_logic_vector(g_adr_b_w-1 downto 0);
+      clock0 : in std_logic;
+      clock1 : in std_logic;
+      data_a : in std_logic_vector(g_dat_a_w-1 downto 0);
+      data_b : in std_logic_vector(g_dat_b_w-1 downto 0);
+      wren_a : in std_logic;
+      wren_b : in std_logic;
+      q_a : out std_logic_vector(g_dat_a_w - 1 downto 0);
+      q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
+  );
+  END COMPONENT;
+
+BEGIN
+
+  -- Copied from ip_arria10_e2sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e2sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+  u_altera_syncram : altera_syncram
+  GENERIC MAP (
+          address_reg_b  => "CLOCK1",
+          clock_enable_input_a  => "BYPASS",
+          clock_enable_input_b  => "BYPASS",
+          clock_enable_output_a  => "BYPASS",
+          clock_enable_output_b  => "BYPASS",
+          indata_reg_b  => "CLOCK1",
+          init_file  => g_init_file,
+          init_file_layout  => "PORT_B",
+          intended_device_family  => "Arria 10",
+          lpm_type  => "altera_syncram",
+          numwords_a  => g_nof_words_a,
+          numwords_b  => g_nof_words_b,
+          operation_mode  => "BIDIR_DUAL_PORT",
+          outdata_aclr_a  => "NONE",
+          outdata_aclr_b  => "NONE",
+          outdata_reg_a  => c_outdata_reg_a,
+          outdata_reg_b  => c_outdata_reg_b,
+          power_up_uninitialized  => "FALSE",
+          read_during_write_mode_port_a  => "NEW_DATA_NO_NBE_READ",
+          read_during_write_mode_port_b  => "NEW_DATA_NO_NBE_READ",
+          widthad_a  => g_adr_a_w,
+          widthad_b  => g_adr_b_w,
+          width_a  => g_dat_a_w,
+          width_b  => g_dat_b_w,
+          width_byteena_a  => 1,
+          width_byteena_b  => 1
+  )
+  PORT MAP (
+      address_a => address_a,
+      address_b => address_b,
+      clock0 => clk_a,
+      clock1 => clk_b,
+      data_a => data_a,
+      data_b => data_b,
+      wren_a => wren_a,
+      wren_b => wren_b,
+      q_a => q_a,
+      q_b => q_b
+  );
+
+END SYN;
+

libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_r_w.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e2sg_ram_r_w IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT (
+    clk         : IN STD_LOGIC  := '1';
+    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+    wren        : IN STD_LOGIC  := '0';
+    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+END ip_arria10_e2sg_ram_r_w;
+
+
+ARCHITECTURE SYN OF ip_arria10_e2sg_ram_r_w IS
+
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+  COMPONENT altera_syncram
+  GENERIC (
+          address_aclr_b  : string;
+          address_reg_b  : string;
+          clock_enable_input_a  : string;
+          clock_enable_input_b  : string;
+          clock_enable_output_b  : string;
+          init_file  : string;
+          intended_device_family  : string;
+          lpm_type  : string;
+          numwords_a  : integer;
+          numwords_b  : integer;
+          operation_mode  : string;
+          outdata_aclr_b  : string;
+          outdata_reg_b  : string;
+          power_up_uninitialized  : string;
+          widthad_a  : integer;
+          widthad_b  : integer;
+          width_a  : integer;
+          width_b  : integer;
+          width_byteena_a  : integer
+  );
+  PORT (
+      address_a : in std_logic_vector(g_adr_w-1 downto 0);
+      address_b : in std_logic_vector(g_adr_w-1 downto 0);
+      clock0 : in std_logic;
+      data_a : in std_logic_vector(g_dat_w-1 downto 0);
+      wren_a : in std_logic;
+      q_b : out std_logic_vector(g_dat_w-1 downto 0)
+  );
+  END COMPONENT;
+
+  SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+  SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+  
+  SIGNAL out_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+  SIGNAL reg_q  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+  
+BEGIN
+
+  ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e2sg_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+  
+  gen_ip : IF g_inferred=FALSE GENERATE
+    -- Copied from ip_arria10_e2sg_ram_r_w/ram_2port_140/sim/ip_arria10_e2sg_ram_r_w_ram_2port_140_hukd7xi.vhd
+    u_altera_syncram : altera_syncram
+    GENERIC MAP (
+            address_aclr_b  => "NONE",
+            address_reg_b  => "CLOCK0",
+            clock_enable_input_a  => "BYPASS",
+            clock_enable_input_b  => "BYPASS",
+            clock_enable_output_b  => "BYPASS",
+            init_file  => g_init_file,
+            intended_device_family  => "Arria 10",
+            lpm_type  => "altera_syncram",
+            numwords_a  => g_nof_words,
+            numwords_b  => g_nof_words,
+            operation_mode  => "DUAL_PORT",
+            outdata_aclr_b  => "NONE",
+            outdata_reg_b  => c_outdata_reg_b,
+            power_up_uninitialized  => "FALSE",
+            widthad_a  => g_adr_w,
+            widthad_b  => g_adr_w,
+            width_a  => g_dat_w,
+            width_b  => g_dat_w,
+            width_byteena_a  => 1
+    )
+    PORT MAP (
+        address_a => wraddress,
+        address_b => rdaddress,
+        clock0 => clk,
+        data_a => data,
+        wren_a => wren,
+        q_b => q
+    );
+  END GENERATE;
+  
+  gen_inferred : IF g_inferred=TRUE GENERATE
+    rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+    wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+  
+    u_mem : entity work.ip_arria10_e2sg_simple_dual_port_ram_single_clock
+    generic map (
+      DATA_WIDTH => g_dat_w,
+      ADDR_WIDTH => g_adr_w
+    )
+    port map (
+      clk   => clk,
+      raddr => rdaddr,
+      waddr => wraddr,
+      data  => data,
+      we    => wren,
+      q     => out_q
+    );
+  
+    reg_q <= out_q WHEN rising_edge(clk);
+    
+    q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
+  END GENERATE;
+   
+END SYN;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_simple_dual_port_ram_dual_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses and
+-- different read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    rclk  : in std_logic;
+    wclk  : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_e2sg_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM signal.  
+  signal ram : memory_t;
+
+begin
+
+  process(wclk)
+  begin
+  if(rising_edge(wclk)) then 
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+  end if;
+  end process;
+
+  process(rclk)
+  begin
+  if(rising_edge(rclk)) then 
+    q <= ram(raddr);
+  end if;
+  end process;
+
+end rtl;

libraries/technology/ip_ultrascale/ram/ip_ultrascale_simple_dual_port_ram_single_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses but
+-- single read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_simple_dual_port_ram_single_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    clk   : in std_logic;
+    raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we    : in std_logic := '1';
+    q   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_e2sg_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_single_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM signal.  
+  signal ram : memory_t;
+
+begin
+
+  process(clk)
+  begin
+  if(rising_edge(clk)) then 
+    if(we = '1') then
+      ram(waddr) <= data;
+    end if;
+ 
+    -- On a read during a write to the same address, the read will
+    -- return the OLD data at the address
+    q <= ram(raddr);
+  end if;
+  end process;
+
+end rtl;
+

libraries/technology/ip_ultrascale/ram/ip_ultrascale_true_dual_port_ram_dual_clock.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- True Dual-Port RAM with dual clock
+--
+-- Read-during-write on port A or B returns newly written data
+-- 
+-- Read-during-write on port A and B returns unknown data.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e2sg_true_dual_port_ram_dual_clock is
+
+  generic 
+  (
+    DATA_WIDTH : natural := 8;
+    ADDR_WIDTH : natural := 6
+  );
+
+  port 
+  (
+    clk_a : in std_logic;
+    clk_b : in std_logic;
+    addr_a  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    addr_b  : in natural range 0 to 2**ADDR_WIDTH - 1;
+    data_a  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    data_b  : in std_logic_vector((DATA_WIDTH-1) downto 0);
+    we_a  : in std_logic := '1';
+    we_b  : in std_logic := '1';
+    q_a   : out std_logic_vector((DATA_WIDTH -1) downto 0);
+    q_b   : out std_logic_vector((DATA_WIDTH -1) downto 0)
+  );
+
+end ip_arria10_e2sg_true_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e2sg_true_dual_port_ram_dual_clock is
+
+  -- Build a 2-D array type for the RAM
+  subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+  -- Declare the RAM 
+  shared variable ram : memory_t;
+
+begin
+
+  -- Port A
+  process(clk_a)
+  begin
+  if(rising_edge(clk_a)) then 
+    if(we_a = '1') then
+      ram(addr_a) := data_a;
+    end if;
+    q_a <= ram(addr_a);
+  end if;
+  end process;
+
+  -- Port B
+  process(clk_b)
+  begin
+  if(rising_edge(clk_b)) then 
+    if(we_b = '1') then
+      ram(addr_b) := data_b;
+    end if;
+    q_b <= ram(addr_b);
+  end if;
+  end process;
+
+end rtl;

libraries/technology/memory/hdllib.cfg

 hdl_lib_name = tech_memory
 hdl_library_clause_name = tech_memory_lib
-hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram
+hdl_lib_uses_synth = technology ip_stratixiv_ram ip_arria10_ram ip_arria10_e3sge3_ram ip_arria10_e1sg_ram ip_arria10_e2sg_ram ip_ultrascale_ram
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 hdl_lib_disclose_library_clause_names =
@@ -9,6 +9,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_ram ip_arria10_e3sge3_ram_lib
     ip_arria10_e1sg_ram   ip_arria10_e1sg_ram_lib
     ip_arria10_e2sg_ram   ip_arria10_e2sg_ram_lib
+    ip_ultrascale_ram     ip_ultrascale_ram_lib
 
 synth_files =
     tech_memory_component_pkg.vhd

libraries/technology/memory/tech_memory_component_pkg.vhd

@@ -516,4 +516,32 @@ PACKAGE tech_memory_component_pkg IS
   );
   END COMPONENT;
 
+  -----------------------------------------------------------------------------
+  -- ip_ultrascale
+  -----------------------------------------------------------------------------
+  COMPONENT ip_ultrascale_ram_crw_crw IS
+  GENERIC (
+    g_inferred   : BOOLEAN := FALSE;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clk_a     : IN STD_LOGIC  := '1';
+    clk_b     : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+
 END tech_memory_component_pkg;

libraries/technology/memory/tech_memory_ram_crw_crw.vhd

@@ -31,6 +31,7 @@ LIBRARY ip_arria10_ram_lib;
 LIBRARY ip_arria10_e3sge3_ram_lib;
 LIBRARY ip_arria10_e1sg_ram_lib;
 LIBRARY ip_arria10_e2sg_ram_lib;
+LIBRARY ip_ultrascale_ram_lib;
 
 ENTITY tech_memory_ram_crw_crw IS
   GENERIC (
@@ -94,5 +95,12 @@ BEGIN
     GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
     PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
   END GENERATE;
+
+  gen_ip_ultrascale : IF g_technology=c_tech_ultrascale GENERATE
+    u0 : ip_ultrascale_ram_crw_crw
+    GENERIC MAP (FALSE, g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+
  
 END ARCHITECTURE;

libraries/technology/technology_pkg.vhd

@@ -49,7 +49,8 @@ PACKAGE technology_pkg IS
   CONSTANT c_tech_arria10_e3sge3     : INTEGER := 6;   -- e.g. used on UniBoard2 second run (7 boards version "01" dec 2015)
   CONSTANT c_tech_arria10_e1sg       : INTEGER := 7;   -- e.g. used on UniBoard2b third run (5 ARTS boards version "01" feb 2017)
   CONSTANT c_tech_arria10_e2sg       : INTEGER := 8;   -- e.g. used on UniBoard2c (2 LOFAR2.0 SDP boards version "11" f 2021)
-  CONSTANT c_tech_nof_technologies   : INTEGER := 9;
+  CONSTANT c_tech_ultrascale         : INTEGER := 9;   -- e.g. used on Alveo FPGA platforms
+  CONSTANT c_tech_nof_technologies   : INTEGER := 10;
 
   -- Functions
   FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING)  RETURN STRING;