singlemac design and IP compiles with Q15.0

boards/uniboard2/designs/unb2_singlemac/build/quartus/unb2_singlemac.qsf

@@ -42,18 +42,24 @@ set_global_assignment -name DEVICE 10AX115U4F45I3SGES
 set_global_assignment -name TOP_LEVEL_ENTITY unb2_singlemac
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:59:19  NOVEMBER 14, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 14.0
+set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name QSYS_FILE ../../../unb2_test/src/ip/system_pll.qsys
-source ../../../../libraries/unb2_board/src/tcl/unb2_all_pins.tcl
+#source ../../../../libraries/unb2_board/src/tcl/unb2_all_pins.tcl
+source ../../../../libraries/unb2_board/quartus/pinning/unb2_all_pins.tcl
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
+
+
+
+
+set_global_assignment -name QSYS_FILE ../../../unb2_singlemac/src/ip/system_pll.qsys
 set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_evt.vhd
 set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/designs/unb_common/src/vhdl/unb_wdi_extend.vhd
 set_global_assignment -name VHDL_FILE ../../../../../../../../UniBoard/trunk/Firmware/modules/common/src/vhdl/common_counter.vhd
@@ -74,7 +80,6 @@ set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_
 set_global_assignment -name VHDL_FILE ../../src/vhdl/unb2_singlemac.vhd
 set_global_assignment -name SDC_FILE ../../src/sdc/unb2_singlemac.sdc
 set_global_assignment -name QSYS_FILE ../../../../../../libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
-
-
+set_global_assignment -name QSYS_FILE system_pll.qsys
+set_global_assignment -name QSYS_FILE ../../src/ip/system_iopll.qsys
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file

boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd

@@ -48,54 +48,54 @@ ENTITY unb2_singlemac IS
     BCK_REF_CLK            : IN    STD_LOGIC; -- SerDes reference clock back
 
     -- SO-DIMM DDR4 Memory Bank i2c (common)
-    MB_SCL                 : inout std_logic;
-    MB_SDA                 : inout std_logic;
+--    MB_SCL                 : inout std_logic;
+--    MB_SDA                 : inout std_logic;
     -- SO-DIMM DDR4 Memory Bank I
-    MB_I_RZQ       : in   STD_LOGIC;
-    MB_I_REF_CLK   : in    STD_LOGIC; -- External reference clock
-    MB_I_A : out std_logic_vector (13 downto 0);
-    MB_I_ACT_N : out std_logic_vector(0 downto 0);
-    MB_I_BA : out std_logic_vector (1 downto 0);
-    MB_I_BG : out std_logic_vector (1 downto 0);
-    MB_I_CAS_A15 : out std_logic;
-    MB_I_CB : inout std_logic_vector (7 downto 0);
-    MB_I_CK : out std_logic_vector (1 downto 0);
-    MB_I_CK_n : out std_logic_vector (1 downto 0);
-    MB_I_CKE : out std_logic_vector (1 downto 0);
-    MB_I_CS : out std_logic_vector (1 downto 0);
-    MB_I_DM : inout std_logic_vector (8 downto 0);
-    MB_I_DQ : inout std_logic_vector (63 downto 0);
-    MB_I_DQS : inout std_logic_vector (8 downto 0);
-    MB_I_DQS_n : inout std_logic_vector (8 downto 0);
-    MB_I_ODT : out std_logic_vector (1 downto 0);
-    MB_I_PARITY : out std_logic_vector(0 downto 0);
-    MB_I_RAS_A16 : out std_logic;
-    MB_I_WE_A14 : out std_logic;
-    MB_I_RESET_N           : out std_logic_vector(0 downto 0);
-    MB_I_ALERT_N           : in std_logic_vector(0 downto 0);
+--    MB_I_RZQ       : in   STD_LOGIC;
+--    MB_I_REF_CLK   : in    STD_LOGIC; -- External reference clock
+--    MB_I_A : out std_logic_vector (13 downto 0);
+--    MB_I_ACT_N : out std_logic_vector(0 downto 0);
+--    MB_I_BA : out std_logic_vector (1 downto 0);
+--    MB_I_BG : out std_logic_vector (1 downto 0);
+--    MB_I_CAS_A15 : out std_logic;
+--    MB_I_CB : inout std_logic_vector (7 downto 0);
+--    MB_I_CK : out std_logic_vector (1 downto 0);
+--    MB_I_CK_n : out std_logic_vector (1 downto 0);
+--    MB_I_CKE : out std_logic_vector (1 downto 0);
+--    MB_I_CS : out std_logic_vector (1 downto 0);
+--    MB_I_DM : inout std_logic_vector (8 downto 0);
+--    MB_I_DQ : inout std_logic_vector (63 downto 0);
+--    MB_I_DQS : inout std_logic_vector (8 downto 0);
+--    MB_I_DQS_n : inout std_logic_vector (8 downto 0);
+--    MB_I_ODT : out std_logic_vector (1 downto 0);
+--    MB_I_PARITY : out std_logic_vector(0 downto 0);
+--    MB_I_RAS_A16 : out std_logic;
+--    MB_I_WE_A14 : out std_logic;
+--    MB_I_RESET_N           : out std_logic_vector(0 downto 0);
+--    MB_I_ALERT_N           : in std_logic_vector(0 downto 0);
     -- SO-DIMM DDR4 Memory Bank II
-    MB_II_RZQ    : in   STD_LOGIC;
-    MB_II_REF_CLK : in    STD_LOGIC; -- External reference clock
-    MB_II_A : out std_logic_vector (13 downto 0);
-    MB_II_ACT_N : out std_logic_vector(0 downto 0);
-    MB_II_BA : out std_logic_vector (1 downto 0);
-    MB_II_BG : out std_logic_vector (1 downto 0);
-    MB_II_CAS_A15 : out std_logic;
-    MB_II_CB : inout std_logic_vector (7 downto 0);
-    MB_II_CK : out std_logic_vector (1 downto 0);
-    MB_II_CK_n : out std_logic_vector (1 downto 0);
-    MB_II_CKE : out std_logic_vector (1 downto 0);
-    MB_II_CS : out std_logic_vector (1 downto 0);
-    MB_II_DM : inout std_logic_vector (8 downto 0); 
-    MB_II_DQ : inout std_logic_vector (63 downto 0);
-    MB_II_DQS : inout std_logic_vector (8 downto 0);
-    MB_II_DQS_n : inout std_logic_vector (8 downto 0);
-    MB_II_ODT : out std_logic_vector (1 downto 0);
-    MB_II_PARITY : out std_logic_vector(0 downto 0);
-    MB_II_RAS_A16 : out std_logic;
-    MB_II_WE_A14 : out std_logic;
-    MB_II_RESET_N          : out std_logic_vector(0 downto 0);
-    MB_II_ALERT_N           : in std_logic_vector(0 downto 0);
+--    MB_II_RZQ    : in   STD_LOGIC;
+--    MB_II_REF_CLK : in    STD_LOGIC; -- External reference clock
+--    MB_II_A : out std_logic_vector (13 downto 0);
+--    MB_II_ACT_N : out std_logic_vector(0 downto 0);
+--    MB_II_BA : out std_logic_vector (1 downto 0);
+--    MB_II_BG : out std_logic_vector (1 downto 0);
+--    MB_II_CAS_A15 : out std_logic;
+--    MB_II_CB : inout std_logic_vector (7 downto 0);
+--    MB_II_CK : out std_logic_vector (1 downto 0);
+--    MB_II_CK_n : out std_logic_vector (1 downto 0);
+--    MB_II_CKE : out std_logic_vector (1 downto 0);
+--    MB_II_CS : out std_logic_vector (1 downto 0);
+--    MB_II_DM : inout std_logic_vector (8 downto 0); 
+--    MB_II_DQ : inout std_logic_vector (63 downto 0);
+--    MB_II_DQS : inout std_logic_vector (8 downto 0);
+--    MB_II_DQS_n : inout std_logic_vector (8 downto 0);
+--    MB_II_ODT : out std_logic_vector (1 downto 0);
+--    MB_II_PARITY : out std_logic_vector(0 downto 0);
+--    MB_II_RAS_A16 : out std_logic;
+--    MB_II_WE_A14 : out std_logic;
+--    MB_II_RESET_N          : out std_logic_vector(0 downto 0);
+--    MB_II_ALERT_N           : in std_logic_vector(0 downto 0);
     
     -- back transceivers
     BCK_SDA : inout std_logic_vector (2 downto 0);
@@ -129,7 +129,7 @@ architecture str of unb2_singlemac is
 
 
 
-   component system_pll is
+   component system_iopll is
      port (
        refclk     : in  std_logic := 'X'; -- clk
        rst        : in  std_logic := 'X';
@@ -138,7 +138,7 @@ architecture str of unb2_singlemac is
        outclk_1   : out std_logic;        -- outclk1
        outclk_2   : out std_logic         -- outclk2
      );
-  end component system_pll;
+  end component system_iopll;
 
   component tech_transceiver_arria10_1 is
     generic (
@@ -256,6 +256,9 @@ architecture str of unb2_singlemac is
     signal qsfp_led_out  : std_logic_vector(11 downto 0);
     signal bck_err_out : std_logic_vector(2 downto 0);
     signal ver_id_pmbusalert     : std_logic_vector(10 downto 0);
+    signal toggle_count     : std_logic_vector(31 downto 0);
+    signal toggle_count1    : std_logic_vector(31 downto 0);
+    signal led_state    : std_logic;
 
 begin
 
@@ -350,7 +353,7 @@ begin
 
     reset_p <= not reset_n;
   
-    u_system_pll : system_pll
+    u_system_pll : system_iopll
       port map(
         refclk   => ETH_CLK,
         rst      => reset_p,
@@ -366,8 +369,8 @@ begin
 
     INTA <= inta_out when PPS = '1' else 'Z';
     INTB <= intb_out when PPS = '1' else 'Z';
-    TESTIO <= testio_out when PPS = '1' else "ZZZZZZ";
-    QSFP_LED <= qsfp_led_out when PPS = '1' else "ZZZZZZZZZZZZ";
+    TESTIO <= testio_out;
+    QSFP_LED <= qsfp_led_out;
     BCK_ERR <= bck_err_out when PPS = '1' else "ZZZ";
 
     inta_in <= INTA;
@@ -378,10 +381,13 @@ begin
     
     inta_out <= intb_in;
     intb_out <= inta_in;
-    testio_out(5 downto 3) <= testio_in(2 downto 0);
-    testio_out(2 downto 0) <= testio_in(5 downto 3);
-    qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
-    qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+    testio_out(5 downto 3) <= (others => '0');
+    testio_out(0) <= CLK;
+    testio_out(1) <= mm_clk;
+--    qsfp_led_out(11 downto 6) <= qsfp_led_in(5 downto 0);
+--    qsfp_led_out(5 downto 0) <= qsfp_led_in(11 downto 6);
+    qsfp_led_out(11 downto 6) <= (others => led_state);
+    qsfp_led_out(5 downto 0) <= (others => not led_state);
     bck_err_out(2) <= bck_err_in(1);
     bck_err_out(1) <= bck_err_in(0);
     bck_err_out(0) <= bck_err_in(2);
@@ -389,4 +395,34 @@ begin
 
     ver_id_pmbusalert <= version & id & pmbus_alert;
 
+    toggle_led_proc: process(mm_clk, reset_p)
+    begin
+      if reset_p = '1' then
+        toggle_count   <= (others => '0');
+        led_state  <= '0';
+      else
+        if mm_clk'event and mm_clk = '1' then
+          if (toggle_count < 100000000) then
+            toggle_count   <= toggle_count + 1;
+          else
+            toggle_count   <= (others => '0');
+	    led_state      <= not led_state;
+          end if;
+        end if;
+      end if;
+    end process;
+
+    toggle_led_proc1: process(clk)
+    begin
+      if clk'event and clk = '1' then
+        if (toggle_count1 < 100000000) then
+          toggle_count1   <= toggle_count1 + 1;
+        else
+          toggle_count1   <= (others => '0');
+          testio_out(2)   <= not testio_out(2);
+	  pout_wdi        <= not pout_wdi;
+        end if;
+      end if;
+    end process;
+
 end str;

libraries/technology/ip_arria10/pll_xgmii_mac_clocks/pll_xgmii_mac_clocks.qsys

@@ -94,7 +94,7 @@
    version="15.0"
    enabled="1"
    autoexport="1">
-  <parameter name="base_device" value="NIGHTFURY5ES" />
+  <parameter name="base_device" value="NIGHTFURY5" />
   <parameter name="enable_bonding_clks" value="0" />
   <parameter name="enable_cascade_in" value="0" />
   <parameter name="enable_fb_comp_bonding" value="0" />

libraries/technology/ip_arria10/transceiver_phy_1/transceiver_phy_1.qsys

@@ -259,7 +259,7 @@
    version="15.0"
    enabled="1"
    autoexport="1">
-  <parameter name="base_device" value="NIGHTFURY5ES" />
+  <parameter name="base_device" value="NIGHTFURY5" />
   <parameter name="bonded_mode" value="not_bonded" />
   <parameter name="cdr_refclk_cnt" value="1" />
   <parameter name="cdr_refclk_select" value="0" />

libraries/technology/ip_arria10/transceiver_pll/transceiver_pll.qsys

@@ -94,7 +94,7 @@
    version="15.0"
    enabled="1"
    autoexport="1">
-  <parameter name="base_device" value="NIGHTFURY5ES" />
+  <parameter name="base_device" value="NIGHTFURY5" />
   <parameter name="bw_sel" value="low" />
   <parameter name="device" value="10AX115U4F45I3SGES" />
   <parameter name="device_family" value="Arria 10" />

libraries/technology/ip_arria10/transceiver_reset_controller_1/transceiver_reset_controller_1.qsys

@@ -28,7 +28,7 @@
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U4F45I3SGES" />
+ <parameter name="device" value="10AX115R4F40I3SG" />
  <parameter name="deviceFamily" value="Arria 10" />
  <parameter name="deviceSpeedGrade" value="3" />
  <parameter name="fabricMode" value="QSYS" />