-Added g_sim and g_sim_level to generics declaration of eth.vhd.

applications/arts/designs/arts_unb1_sc1_bg_1GbE/src/vhdl/arts_unb1_sc1_bg_1GbE.vhd

@@ -279,6 +279,7 @@ BEGIN
   GENERIC MAP (
     g_technology              => c_technology,
     g_sim                     => g_sim,
+    g_sim_level               => 1, -- Use fast behavioural model as we use eth_statistics in the test bench.
     g_design_name             => c_ctrl_unb1_board_design_name,
     g_stamp_date              => c_ctrl_unb1_board_stamp_date,
     g_stamp_time              => c_ctrl_unb1_board_stamp_time, 

boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd

@@ -44,6 +44,7 @@ ENTITY ctrl_unb1_board IS
     ----------------------------------------------------------------------------
     g_technology      : NATURAL := c_tech_stratixiv;
     g_sim             : BOOLEAN := FALSE;
+    g_sim_level       : NATURAL := 0;
     g_sim_flash_model : BOOLEAN := FALSE;  -- only maximum one instance should have the flash model (see mms_epcs.vhd description)
     g_base_ip         : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
     g_design_name     : STRING := "UNUSED  "; 
@@ -60,7 +61,7 @@ ENTITY ctrl_unb1_board IS
     ----------------------------------------------------------------------------
     g_dp_clk_freq    : NATURAL := c_unb1_board_ext_clk_freq_200M;
     g_dp_clk_use_pll : BOOLEAN := TRUE;
-    -- PLL phase clk shift with respect to CLK
+    -- PLL phase clk shift with respect to CL
     --     STRING :=    "0"             = 0
     --     STRING :=  "156"             = 011.25
     --     STRING :=  "313"             = 022.5 
@@ -658,7 +659,9 @@ BEGIN
     GENERIC MAP (
       g_technology         => g_technology,
       g_init_ip_address    => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
-      g_cross_clock_domain => g_udp_offload
+      g_cross_clock_domain => g_udp_offload,
+      g_sim                => g_sim,
+      g_sim_level          => g_sim_level
     )
     PORT MAP (
       -- Clocks and reset

libraries/io/eth/src/vhdl/eth.vhd

@@ -46,7 +46,9 @@ ENTITY eth IS
     g_cross_clock_domain : BOOLEAN := TRUE;    -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
     g_ETH_PHY            : STRING  := "LVDS";  -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
     g_ihl20              : BOOLEAN := FALSE;
-    g_frm_discard_en     : BOOLEAN := FALSE     -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+    g_frm_discard_en     : BOOLEAN := FALSE;    -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
+    g_sim                : BOOLEAN := FALSE;
+    g_sim_level          : NATURAL := 0 -- 0=IP, 1=behavioural model
   );
   PORT (
     -- Clocks and reset
@@ -632,7 +634,11 @@ BEGIN
   u_tech_tse : ENTITY tech_tse_lib.tech_tse
   GENERIC MAP (
     g_technology   => g_technology,
-    g_ETH_PHY      => g_ETH_PHY
+    g_ETH_PHY      => g_ETH_PHY,
+    g_sim          => TRUE,
+    g_sim_level    => g_sim_level,
+    g_sim_tx       => TRUE,
+    g_sim_rx       => sel_a_b(g_sim_level=1, FALSE, TRUE) -- TX only when using fast behavioural model
   )
   PORT MAP (
     -- Clocks and reset