Added more comment to clarify signals.

libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd

@@ -29,9 +29,16 @@
 --   sop and eop will be active.
 --   Alternatively, one can assert dp_on while dp_on_pps is high to 
 --   start the data path on the next PPS.
+--   The dp_on is asynchronous. The dp_bsn_source_v2 takes care that
+--   src_out.valid starts with a src_out.sop and that src_out.valid can
+--   only go low after a src_out.eop, to ensure that src_out only produces
+--   complete sop-eop blocks that enter the subsequent processing.
+--   The bs_start is active at the first src_out.sop after dp_on went high.
 -- Remarks:
---   Starting the data path is only possible from the dp_off state, so one
+-- . Starting the data path is only possible from the dp_off state, so one
 --   has to disable (dp_on='0') the data path before restarting it.
+-- . Effectively dp_on_status = src_out.valid, because when the BSN source
+--   is on, then src_out.valid = '1' at every clk cycle.
 --
 -- author : P.Donker  okt. 2020, added bsn_time_offset
 --
@@ -57,8 +64,8 @@ ENTITY dp_bsn_source_v2 IS
     dp_on                   : IN  STD_LOGIC;
     dp_on_pps               : IN  STD_LOGIC;
 
-    dp_on_status            : OUT STD_LOGIC;
-    bs_restart              : OUT STD_LOGIC;
+    dp_on_status            : OUT STD_LOGIC;  -- = src_out.valid
+    bs_restart              : OUT STD_LOGIC;  -- = src_out.sop for first sop after dp_on went high
  
     nof_clk_per_sync        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
     bsn_init                : IN  STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');