Added two signals for calibration status

libraries/base/common/src/vhdl/common_mem_pkg.vhd

@@ -106,6 +106,8 @@ PACKAGE common_mem_pkg IS
     rdval         : STD_LOGIC;
     waitrequest_n : STD_LOGIC;  -- comparable to DP siso.ready
     done          : STD_LOGIC;  -- comparable to DP siso.xon, not part of Avalon bus, can eg. act as init done or init ok or ready for next block, useful for DDR controller
+    cal_ok        : STD_LOGIC;
+    cal_fail      : STD_LOGIC;
   END RECORD;
   
   TYPE t_mem_ctlr_mosi IS RECORD  
@@ -118,7 +120,7 @@ PACKAGE common_mem_pkg IS
     flush         : STD_LOGIC;  -- not part of Avalon bus, but useful for DDR driver
   END RECORD;
   
-  CONSTANT c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((OTHERS=>'0'), '0', '0', '0');
+  CONSTANT c_mem_ctlr_miso_rst : t_mem_ctlr_miso := ((OTHERS=>'0'), '0', '0', '0', '0', '0');
   CONSTANT c_mem_ctlr_mosi_rst : t_mem_ctlr_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', (OTHERS=>'0'), '0');
 
   -- Multi port array for mem_ctlr records