Add rsn to sensitivity list.

libraries/base/dp/src/vhdl/dp_rsn_source.vhd

@@ -56,22 +56,22 @@ USE work.dp_stream_pkg.ALL;
 
 ENTITY dp_rsn_source IS
   GENERIC (
-    g_block_size         : NATURAL := 256;  -- >= 3, see state machine
-    g_nof_clk_per_sync   : NATURAL := 200 * 10**6;
-    g_bsn_w              : NATURAL := 64
+    g_block_size        : NATURAL := 256;  -- >= 3, see state machine
+    g_nof_clk_per_sync  : NATURAL := 200 * 10**6;
+    g_bsn_w             : NATURAL := 64
   );
   PORT (
-    rst                     : IN  STD_LOGIC;
-    clk                     : IN  STD_LOGIC;
+    rst                 : IN  STD_LOGIC;
+    clk                 : IN  STD_LOGIC;
 
     -- Input stream sosi control using BSN
-    bs_sosi                 : IN  t_dp_sosi;  -- input reference stream using BSN
+    bs_sosi             : IN  t_dp_sosi;  -- input reference stream using BSN
 
     -- Output stream sosi control using RSN
-    nof_clk_per_sync        : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
-    rs_sosi                 : OUT t_dp_sosi;  -- output stream using RSN and g_block_size, g_nof_clk_per_sync
-    rs_restart              : OUT STD_LOGIC;  -- = rs_sosi.sync for first sync after bs_sosi.valid went high
-    rs_new_interval         : OUT STD_LOGIC   -- = active during first rs_sosi.sync interval
+    nof_clk_per_sync    : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
+    rs_sosi             : OUT t_dp_sosi;  -- output stream using RSN and g_block_size, g_nof_clk_per_sync
+    rs_restart          : OUT STD_LOGIC;  -- = rs_sosi.sync for first sync after bs_sosi.valid went high
+    rs_new_interval     : OUT STD_LOGIC   -- = active during first rs_sosi.sync interval
   );
 END dp_rsn_source;
 
@@ -79,6 +79,7 @@ END dp_rsn_source;
 ARCHITECTURE rtl OF dp_rsn_source IS
 
   CONSTANT c_block_size_cnt_w : NATURAL := ceil_log2(g_block_size);
+  CONSTANT c_rsn_product_w    : NATURAL := g_bsn_w + c_block_size_cnt_w;
 
   TYPE t_state_enum IS (s_off, s_on_sop, s_on, s_on_eop);
 
@@ -86,7 +87,7 @@ ARCHITECTURE rtl OF dp_rsn_source IS
   SIGNAL nxt_state   : t_state_enum; 
   SIGNAL prev_state  : t_state_enum;
 
-  SIGNAL rsn                 : STD_LOGIC_VECTOR(g_bsn_w + c_block_size_cnt_w - 1 DOWNTO 0);
+  SIGNAL rsn                 : STD_LOGIC_VECTOR(c_rsn_product_w-1 DOWNTO 0);
 
   SIGNAL nxt_sync            : STD_LOGIC;
   SIGNAL sync                : STD_LOGIC;
@@ -110,11 +111,11 @@ BEGIN
   rs_restart <= i_rs_restart;
   rs_new_interval <= i_rs_new_interval;
 
-  -- Use sum of inputs nof bits for product, but actual RSN fits in g_bsn_w.
   rsn <= MULT_UVEC(bs_sosi.bsn, TO_UVEC(g_block_size, c_block_size_cnt_w));
 
   p_state : PROCESS(sync, sync_size_cnt, nof_clk_per_sync,
-                    state, prev_state, i_rs_sosi, block_size_cnt)
+                    state, prev_state,
+                    i_rs_sosi, block_size_cnt, rsn)
   BEGIN  
     -- Maintain sync_size_cnt for nof_clk_per_sync
     -- . nof_clk_per_sync is the number of clk per sync interval and the
@@ -143,7 +144,7 @@ BEGIN
     CASE state IS
       WHEN s_off =>
         nxt_rs_sosi <= c_dp_sosi_rst;
-        nxt_rs_sosi.bsn <= rsn(g_bsn_w-1 DOWNTO 0);  -- RSN
+        nxt_rs_sosi.bsn <= rsn(g_bsn_w-1 DOWNTO 0);  -- RSN fits in g_bsn_w
         nxt_sync <= '0';
         nxt_sync_size_cnt <= (OTHERS=>'0');
         IF bs_sosi.sync = '1' THEN