initial commit of dp_block_validate_length

libraries/base/dp/hdllib.cfg

@@ -30,6 +30,7 @@ synth_files =
     src/vhdl/dp_pipeline_arr.vhd
     src/vhdl/dp_pipeline_ready.vhd
     src/vhdl/dp_block_resize.vhd
+    src/vhdl/dp_block_validate_length.vhd
     src/vhdl/dp_block_select.vhd
     src/vhdl/mms_dp_block_select.vhd
     src/vhdl/dp_force_data_parallel.vhd
@@ -193,6 +194,7 @@ test_bench_files =
     tb/vhdl/dp_stream_verify.vhd
     
     tb/vhdl/tb_dp_block_select.vhd
+    tb/vhdl/tb_dp_block_validate_length.vhd
     tb/vhdl/tb_dp_block_reshape.vhd
     tb/vhdl/tb_dp_block_reshape_sync.vhd
     tb/vhdl/tb_dp_block_gen.vhd

libraries/base/dp/src/vhdl/dp_block_validate_length.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author: R vd Walle
+-- Purpose:
+--   Validate the length of a DP block.
+-- Description:
+-- The dp_block_validate_length.vhd checks whether the in_sosi block has the 
+-- expected length given by g_expected_length. The block length is defined by 
+-- the number of valid from sop to eop. The tasks of the 
+-- dp_block_validate_length.vhd are:
+-- . Default all in_sosi fields are passed on to the out_sosi.
+-- . If the input block length differs from g_expected_length, then the bit at
+--   bit index g_err_bi in the out_sosi.err field is forced to 1, else the 
+--   out_sosi.err field passes on the in_sosi.err field.
+-- . If the input block length > g_expected_length, then the out_sosi block 
+--   length is restricted to g_expected_length, by inserting an eop and 
+--   discarding the remaining data and eop information from the in_sosi.
+-- Remarks:
+-- - This component supports flow control and was designed by keeping the functional
+--   state registers and the pipeline registers seperate. Therefore the function is 
+--   implemented using combinatorial logic and local state registers to keep its
+--   state. The combinatorial function output preserves the snk_in ready latency and
+--   is pipelined using dp_pipeline to ease timing closure on the output.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.all;
+USE work.dp_stream_pkg.ALL;
+
+ENTITY dp_block_validate_length IS
+  GENERIC (
+    g_err_bi          : NATURAL := 0;   -- bit index in error field
+    g_expected_length : NATURAL := 255 
+  );
+  PORT (
+    rst          : IN  STD_LOGIC;
+    clk          : IN  STD_LOGIC;
+    -- ST sink
+    snk_out      : OUT t_dp_siso;
+    snk_in       : IN  t_dp_sosi;
+    -- ST source
+    src_in       : IN  t_dp_siso := c_dp_siso_rdy;
+    src_out      : OUT t_dp_sosi
+  );
+END dp_block_validate_length;
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.all;
+USE work.dp_stream_pkg.ALL;
+
+ARCHITECTURE rtl OF dp_block_validate_length IS
+
+  SIGNAL cnt_reg      : NATURAL;
+  SIGNAL cnt          : NATURAL;
+  SIGNAL block_sosi   : t_dp_sosi;
+  
+BEGIN
+
+  p_clk : PROCESS(rst, clk)
+  BEGIN
+    IF rst='1' THEN
+      cnt_reg      <= 0;
+    ELSIF rising_edge(clk) THEN
+      cnt_reg      <= cnt;
+    END IF;
+  END PROCESS;
+
+  -- Count valid per block
+  p_cnt : PROCESS(snk_in, cnt_reg)
+  BEGIN
+    cnt <= cnt_reg;
+    IF snk_in.sop='1' THEN
+      cnt <= 0;
+    ELSIF snk_in.valid='1' THEN
+      cnt <= cnt_reg + 1;
+    END IF;
+  END PROCESS;
+
+  -- Resize snk_in combinatorially into block_sosi, so no impact on RL
+  p_block_sosi : PROCESS(snk_in, cnt)
+  BEGIN
+    -- Default keep snk_in info and data fields
+    block_sosi       <= snk_in;
+    IF snk_in.valid='1' THEN
+      -- Set output eop, info @ eop gets lost if g_expected_length < actual block size
+      IF NOT(snk_in.eop = '1' AND cnt = g_expected_length-1) THEN
+        block_sosi.eop           <= '1';
+        block_sosi.err(g_err_bi) <= '1';
+      END IF;
+        
+      IF cnt = g_expected_length-1 THEN
+        block_sosi.eop   <= '1';
+      END IF;
+
+      IF cnt > g_expected_length THEN
+        block_sosi <= c_dp_sosi_rst;
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Register block_sosi to easy timing closure
+  u_pipeline : ENTITY work.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => 1  -- 0 for wires, > 0 for registers, 
+  )
+  PORT MAP (
+    rst          => rst,
+    clk          => clk,
+    -- ST sink
+    snk_out      => snk_out,
+    snk_in       => block_sosi,
+    -- ST source
+    src_in       => src_in,
+    src_out      => src_out
+  );
+  
+END rtl;

libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author:
+--   Eric Kooistra, 26 Apr 2018
+-- Purpose:
+-- . Test bench for dp_block_resize.
+-- Description:
+--   Block diagram:
+--
+--    stimuli --> dp_block_resize -- > verify
+--   
+-- Remark:
+-- . Pipelining and flow control are already covered by tb_dp_pipeline.vhd.
+--   
+-- Usage:
+-- . as 5
+-- . run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+ENTITY tb_dp_block_validate_length IS
+  GENERIC (
+    g_nof_blocks_per_sync  : NATURAL := 5;
+    g_index_lo             : NATURAL := 0;
+    g_expected_length             : NATURAL := 3
+  );
+END tb_dp_block_validate_length;
+
+
+ARCHITECTURE tb OF tb_dp_block_validate_length IS
+
+  ------------------------------------------------------------------------------
+  -- Clock & reset
+  ------------------------------------------------------------------------------
+  CONSTANT c_clk_period  : TIME := 5 ns;
+
+  CONSTANT c_dut_pipeline             : NATURAL := 1;
+  CONSTANT c_nof_sync                 : NATURAL := 5;
+  CONSTANT c_gap_size                 : NATURAL := 4;
+  CONSTANT c_nof_data_per_blk         : NATURAL := 9; 
+  
+  SIGNAL clk            : STD_LOGIC := '1';
+  SIGNAL rst            : STD_LOGIC := '1';
+  SIGNAL tb_end         : STD_LOGIC := '0';
+  
+  SIGNAL stimuli_end         : STD_LOGIC;
+  SIGNAL stimuli_sosi        : t_dp_sosi;
+  SIGNAL stimuli_siso        : t_dp_siso;
+  SIGNAL stimuli_blk_cnt_reg : NATURAL;
+  SIGNAL stimuli_blk_cnt     : NATURAL;
+  SIGNAL verify_sosi         : t_dp_sosi;
+  SIGNAL verify_siso         : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL reference_blk_cnt   : NATURAL;
+  SIGNAL reference_sosi      : t_dp_sosi;
+  SIGNAL reference_siso      : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL sync_sosi           : t_dp_sosi;
+  
+BEGIN
+  
+  ------------------------------------------------------------------------------
+  -- Clock & reset
+  ------------------------------------------------------------------------------
+  clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+  rst <= '1', '0' AFTER c_clk_period*7;
+  
+  ------------------------------------------------------------------------------
+  -- Stimuli: 
+  ------------------------------------------------------------------------------
+
+  -- Generate snk_in with data frames
+  u_stimuli : ENTITY work.dp_stream_stimuli
+  GENERIC MAP (
+    g_sync_period => g_nof_blocks_per_sync,
+    g_nof_repeat  => g_nof_blocks_per_sync * c_nof_sync,
+    g_pkt_len     => c_nof_data_per_blk,
+    g_pkt_gap     => c_gap_size
+  )
+  PORT MAP (
+    rst               => rst,
+    clk               => clk,
+  
+    -- Generate stimuli
+    src_in            => stimuli_siso,
+    src_out           => stimuli_sosi,
+
+    -- End of stimuli
+    tb_end            => stimuli_end
+  );
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------     
+  u_select : ENTITY work.dp_block_validate_length
+  GENERIC MAP (
+    g_expected_length  => g_expected_length
+  )
+  PORT MAP (
+    rst          => rst,
+    clk          => clk,
+    -- ST sink
+    snk_out      => stimuli_siso,
+    snk_in       => stimuli_sosi,
+    -- ST source
+    src_in       => verify_siso,
+    src_out      => verify_sosi
+  );
+
+  
+  ------------------------------------------------------------------------------
+  -- Verification
+  ------------------------------------------------------------------------------
+  
+  u_pipeline : ENTITY work.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => c_dut_pipeline
+  )
+  PORT MAP (
+    rst         => rst,
+    clk         => clk,
+    -- ST sink
+    snk_out     => OPEN,
+    snk_in      => stimuli_sosi,
+    -- ST source
+    src_in      => reference_siso,
+    src_out     => reference_sosi 
+  );
+  
+  stimuli_blk_cnt_reg <= stimuli_blk_cnt WHEN rising_edge(clk);
+  stimuli_blk_cnt <= 0                       WHEN stimuli_sosi.sync='1' ELSE
+                     stimuli_blk_cnt_reg + 1 WHEN stimuli_sosi.sop='1' ELSE
+                     stimuli_blk_cnt_reg;
+  
+  -- Only support c_dut_pipeline = 0 or 1
+  reference_blk_cnt <= stimuli_blk_cnt WHEN c_dut_pipeline=0 ELSE
+                       stimuli_blk_cnt WHEN rising_edge(clk);
+                       
+  -- Keep BSN at sync
+  sync_sosi <= reference_sosi WHEN  rising_edge(clk) AND reference_sosi.sync='1';
+  
+  p_verify : PROCESS(clk)
+  BEGIN
+    IF rising_edge(clk) THEN
+      IF reference_sosi.valid='1' THEN
+        IF reference_blk_cnt<=g_expected_length AND reference_blk_cnt < g_nof_blocks_per_sync THEN
+          ---------------------------------------------------------------------
+          -- Selected blocks
+          ---------------------------------------------------------------------
+          -- Direct sosi verification because sync and BSN are not moved when g_index_lo=0
+          ASSERT verify_sosi=reference_sosi REPORT "Wrong selected subsequent blocks" SEVERITY ERROR;
+        ELSE
+          ---------------------------------------------------------------------
+          -- Skipped blocks
+          ---------------------------------------------------------------------
+          ASSERT verify_sosi.sync='0'  REPORT "Wrong skipped sync"  SEVERITY ERROR;
+          ASSERT verify_sosi.valid='0' REPORT "Wrong skipped valid" SEVERITY ERROR;
+          ASSERT verify_sosi.sop='0'   REPORT "Wrong skipped sop"   SEVERITY ERROR;
+          ASSERT verify_sosi.eop='0'   REPORT "Wrong skipped eop"   SEVERITY ERROR;
+        END IF;
+      END IF;
+    END IF;
+  END PROCESS;
+  
+  tb_end <= '0', stimuli_end AFTER (1 + 10*c_dut_pipeline)*c_clk_period;
+  
+END tb;