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applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_13/src/vhdl/bunny_static_split2rtl_hwn_nd_13.vhd

@@ -43,11 +43,11 @@ entity bunny_static_split2rtl_hwn_nd_13 is
       -- Dataflow Control Input interfaces
       -- Dataflow output interfaces
       -- ED_19_20 : out_0
-      ND_13OP_1_d1_ND_13OP_1_Wr   : out std_logic;
-      ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
-      ND_13OP_1_d1_ND_13OP_1_Full : in  std_logic;
-      ND_13OP_1_d1_ND_13OP_1_CLK  : out std_logic;
-      ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+      ND_13OP_1_ND_13OP_1_d1_Wr   : out std_logic;
+      ND_13OP_1_ND_13OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+      ND_13OP_1_ND_13OP_1_d1_Full : in  std_logic;
+      ND_13OP_1_ND_13OP_1_d1_CLK  : out std_logic;
+      ND_13OP_1_ND_13OP_1_d1_CTRL : out std_logic;
 
       PARAM_DT : in  std_logic_vector(PAR_WIDTH+10-1 downto 0);
       PARAM_LD : in  std_logic;
@@ -313,7 +313,7 @@ begin
    sl_RST <= RST when RESET_HIGH=1 else not RST;
       ND_13IP_17_CLK   <= CLK;
       ND_13IP_18_CLK   <= CLK;
-      ND_13OP_1_d1_ND_13OP_1_CLK  <= CLK;
+      ND_13OP_1_ND_13OP_1_d1_CLK  <= CLK;
 
    --
    -- ==========================================================
@@ -425,10 +425,10 @@ begin
       WRITE_ST => sl_write_st(0)
    );
    --
-   ND_13OP_1_d1_ND_13OP_1_Dout <= sl_out_port_0;  -- Func. Output param. "result"
-   ND_13OP_1_d1_ND_13OP_1_CTRL <= sl_sof_wr ;
-   ND_13OP_1_d1_ND_13OP_1_Wr   <= sl_WRITES(0);
-   sl_FULLS(0) <= ND_13OP_1_d1_ND_13OP_1_Full;
+   ND_13OP_1_ND_13OP_1_d1_Dout <= sl_out_port_0;  -- Func. Output param. "result"
+   ND_13OP_1_ND_13OP_1_d1_CTRL <= sl_sof_wr ;
+   ND_13OP_1_ND_13OP_1_d1_Wr   <= sl_WRITES(0);
+   sl_FULLS(0) <= ND_13OP_1_ND_13OP_1_d1_Full;
    sl_lortnoc_wr(0) <= sl_control_wr(0);
    --
    --

applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14.vhd

@@ -27,11 +27,11 @@ entity bunny_static_split2rtl_hwn_nd_14 is
 
       -- Dataflow input interfaces
       -- ED_19_20 : in_0
-      ND_14IP_20_ND_14IP_19_Rd    : out std_logic;
-      ND_14IP_20_ND_14IP_19_Din   : in  std_logic_vector(63 downto 0);
-      ND_14IP_20_ND_14IP_19_Exist : in  std_logic; 
-      ND_14IP_20_ND_14IP_19_CLK   : out std_logic;
-      ND_14IP_20_ND_14IP_19_CTRL  : in  std_logic;
+      ND_14IP_19_ND_14IP_20_Rd    : out std_logic;
+      ND_14IP_19_ND_14IP_20_Din   : in  std_logic_vector(63 downto 0);
+      ND_14IP_19_ND_14IP_20_Exist : in  std_logic; 
+      ND_14IP_19_ND_14IP_20_CLK   : out std_logic;
+      ND_14IP_19_ND_14IP_20_CTRL  : in  std_logic;
 
       -- ED_21 : in_0
       ND_14IP_21_Rd    : out std_logic;
@@ -307,7 +307,7 @@ architecture RTL of bunny_static_split2rtl_hwn_nd_14 is
 begin 
 
    sl_RST <= RST when RESET_HIGH=1 else not RST;
-      ND_14IP_20_ND_14IP_19_CLK   <= CLK;
+      ND_14IP_19_ND_14IP_20_CLK   <= CLK;
       ND_14IP_21_CLK   <= CLK;
       data_out_CLK  <= CLK;
 
@@ -340,13 +340,13 @@ begin
       RELEASE    => sl_release_rd(1 downto 0)
    );
 
-   ND_14IP_20_ND_14IP_19_Rd   <= sl_READS(0);
+   ND_14IP_19_ND_14IP_20_Rd   <= sl_READS(0);
    ND_14IP_21_Rd   <= sl_READS(1);
 
-   sl_IN_PORTS_0 <= ND_14IP_21_Din & ND_14IP_20_ND_14IP_19_Din;
+   sl_IN_PORTS_0 <= ND_14IP_21_Din & ND_14IP_19_ND_14IP_20_Din;
 
-   sl_EXISTS      <= ND_14IP_21_Exist & ND_14IP_20_ND_14IP_19_Exist ;
-   sl_CTRLS       <= ND_14IP_21_CTRL & ND_14IP_20_ND_14IP_19_CTRL ;
+   sl_EXISTS      <= ND_14IP_21_Exist & ND_14IP_19_ND_14IP_20_Exist ;
+   sl_CTRLS       <= ND_14IP_21_CTRL & ND_14IP_19_ND_14IP_20_CTRL ;
 
    EVAL_RD : bunny_static_split2rtl_EVAL_LOGIC_RD_hwn_nd_14
    generic map ( 

applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/hwn_nd_14/src/vhdl/bunny_static_split2rtl_hwn_nd_14_eval_logic_rd.vhd

@@ -186,7 +186,7 @@ begin
 
    sl_fire <= ('1');
 
-   -- Convert FIFO Read Port ND_14IP_20_ND_14IP_19 Argument in_1 : ED_19_20 : 0 of type IOMM
+   -- Convert FIFO Read Port ND_14IP_19_ND_14IP_20 Argument in_1 : ED_19_20 : 0 of type IOMM
    sl_obtain0 <= ('1');  -- set obtain/release to const value; not used
    sl_release0 <= ('1');
 

applications/compaan/libraries/bunny_static_split/compaandesign_com/bunny_static_split2rtl/register_rf/src/vhdl/register_rf.vhd

@@ -5,9 +5,8 @@ use ieee.numeric_std.all;
 
 entity register_rf is
  generic (
-	C_commit_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000000"; -- 0
-	C_brightness_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000100"; -- 4
-	C_count_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000001000" -- 8
+	C_brightness_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000000"; -- 0
+	C_count_rf_address   : std_logic_vector(18 downto 0) := B"0000000000000000100" -- 4
  );
 
 port (
@@ -23,13 +22,6 @@ port (
 	write_en        : in std_logic;
 	write_data      : in std_logic_vector(31 downto 0);
 	--
-	-- Interface to reg commit
-	commit_rf_read_data       : in std_logic_vector(32-1 downto 0);
-	commit_rf_read_en         : out std_logic;
-	commit_rf_write_en        : out std_logic;
-	commit_rf_write_data      : out std_logic_vector(32-1 downto 0);
-	--
- 
 	-- Interface to reg brightness
 	brightness_rf_read_data       : in std_logic_vector(32-1 downto 0);
 	brightness_rf_read_en         : out std_logic;
@@ -51,31 +43,6 @@ architecture RTL of register_rf is
 	signal sl_read_data : std_logic_vector(32-1 downto 0)   := (others=>'0');
  
 begin
-process (pci_clk,rst)
-	begin
-		if (rising_edge(pci_clk)) then
-			if (rst = '1') then
-				commit_rf_write_en <= '0';
-				commit_rf_read_en  <= '0';
-				commit_rf_write_data  <= (others => '0');
-			else
-
-				if ( (address(18 downto 2) = C_commit_rf_address(18 downto 2)) and write_en = '1') then
-						commit_rf_write_data <= write_data(32-1 downto 0);
-						commit_rf_write_en <= '1';
-				else
-					commit_rf_write_en <= '0';
-				end if;
-
-				if( (address(18 downto 2) = C_commit_rf_address(18 downto 2)) and read_en= '1') then
-					commit_rf_read_en <= '1';
-				else
-					commit_rf_read_en <= '0';
-				end if;
-		end if;
-	end if;
-end process;
-
 process (pci_clk,rst)
 	begin
 		if (rising_edge(pci_clk)) then
@@ -132,8 +99,6 @@ begin
      if (rst = '1') then
 	  else
 	    case  address(18 downto 2)  is
-			when (C_commit_rf_address(18 downto 2) ) =>
-			  sl_read_data(32-1 downto 0) <=   commit_rf_read_data;
 			when (C_brightness_rf_address(18 downto 2) ) =>
 			  sl_read_data(32-1 downto 0) <=   brightness_rf_read_data;
 			when (C_count_rf_address(18 downto 2) ) =>

applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split.vhd

@@ -391,11 +391,11 @@ architecture STRUCTURE of bunny_static_split is
 		ND_13IP_18_CLK : out std_logic;
 		ND_13IP_18_CTRL : in std_logic;
 
-		ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
-		ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
-		ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
-		ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
-		ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_Wr : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+		ND_13OP_1_ND_13OP_1_d1_Full : in std_logic;
+		ND_13OP_1_ND_13OP_1_d1_CLK : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_CTRL : out std_logic;
 
 		PARAM_DT : in std_logic_vector(10 downto 0);
 		PARAM_LD : in std_logic;
@@ -410,11 +410,11 @@ architecture STRUCTURE of bunny_static_split is
 
   component bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
     port (
-		ND_14IP_20_ND_14IP_19_Rd : out std_logic;
-		ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
-		ND_14IP_20_ND_14IP_19_Exist : in std_logic;
-		ND_14IP_20_ND_14IP_19_CLK : out std_logic;
-		ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+		ND_14IP_19_ND_14IP_20_Rd : out std_logic;
+		ND_14IP_19_ND_14IP_20_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_19_ND_14IP_20_Exist : in std_logic;
+		ND_14IP_19_ND_14IP_20_CLK : out std_logic;
+		ND_14IP_19_ND_14IP_20_CTRL : in std_logic;
 
 		ND_14IP_21_Rd : out std_logic;
 		ND_14IP_21_Din : in std_logic_vector(63 downto 0);
@@ -1515,11 +1515,11 @@ begin
 		ND_13IP_18_Exist => signal_ed_18_in_FSL_S_Exists,
 		ND_13IP_18_CLK => open,
 		ND_13IP_18_CTRL => signal_ed_18_in_FSL_S_Control,
-		ND_13OP_1_d1_ND_13OP_1_Wr => signal_ed_19_20_out_FSL_M_Write,
-		ND_13OP_1_d1_ND_13OP_1_Dout(63 downto 0) => signal_ed_19_20_out_FSL_M_Data(0 to 63),
-		ND_13OP_1_d1_ND_13OP_1_Full => signal_ed_19_20_out_FSL_M_Full,
-		ND_13OP_1_d1_ND_13OP_1_CLK => open,
-		ND_13OP_1_d1_ND_13OP_1_CTRL => signal_ed_19_20_out_FSL_M_Control,
+		ND_13OP_1_ND_13OP_1_d1_Wr => signal_ed_19_20_out_FSL_M_Write,
+		ND_13OP_1_ND_13OP_1_d1_Dout(63 downto 0) => signal_ed_19_20_out_FSL_M_Data(0 to 63),
+		ND_13OP_1_ND_13OP_1_d1_Full => signal_ed_19_20_out_FSL_M_Full,
+		ND_13OP_1_ND_13OP_1_d1_CLK => open,
+		ND_13OP_1_ND_13OP_1_d1_CTRL => signal_ed_19_20_out_FSL_M_Control,
 		PARAM_DT => signal_PARAM_DT,
 		PARAM_LD => signal_PARAM_LD,
 		STOP => signal_hwn_nd_13_STOP,
@@ -1531,11 +1531,11 @@ begin
 
   bunny_static_split2rtl_hwn_nd_14_ip : bunny_static_split2rtl_hwn_nd_14_ip_wrapper
 	port map (
-		ND_14IP_20_ND_14IP_19_Rd => signal_ed_19_20_in_FSL_S_Read,
-		ND_14IP_20_ND_14IP_19_Din(63 downto 0) => signal_ed_19_20_in_FSL_S_Data(0 to 63),
-		ND_14IP_20_ND_14IP_19_Exist => signal_ed_19_20_in_FSL_S_Exists,
-		ND_14IP_20_ND_14IP_19_CLK => open,
-		ND_14IP_20_ND_14IP_19_CTRL => signal_ed_19_20_in_FSL_S_Control,
+		ND_14IP_19_ND_14IP_20_Rd => signal_ed_19_20_in_FSL_S_Read,
+		ND_14IP_19_ND_14IP_20_Din(63 downto 0) => signal_ed_19_20_in_FSL_S_Data(0 to 63),
+		ND_14IP_19_ND_14IP_20_Exist => signal_ed_19_20_in_FSL_S_Exists,
+		ND_14IP_19_ND_14IP_20_CLK => open,
+		ND_14IP_19_ND_14IP_20_CTRL => signal_ed_19_20_in_FSL_S_Control,
 		ND_14IP_21_Rd => signal_ed_21_in_FSL_S_Read,
 		ND_14IP_21_Din(63 downto 0) => signal_ed_21_in_FSL_S_Data(0 to 63),
 		ND_14IP_21_Exist => signal_ed_21_in_FSL_S_Exists,

applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_13_ip_wrapper.vhd

@@ -24,11 +24,11 @@ entity bunny_static_split2rtl_hwn_nd_13_ip_wrapper is
     ND_13IP_18_Exist : in std_logic;
     ND_13IP_18_CLK : out std_logic;
     ND_13IP_18_CTRL : in std_logic;
-    ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
-    ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
-    ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
-    ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
-    ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+    ND_13OP_1_ND_13OP_1_d1_Wr : out std_logic;
+    ND_13OP_1_ND_13OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+    ND_13OP_1_ND_13OP_1_d1_Full : in std_logic;
+    ND_13OP_1_ND_13OP_1_d1_CLK : out std_logic;
+    ND_13OP_1_ND_13OP_1_d1_CTRL : out std_logic;
     PARAM_DT : in std_logic_vector(10 downto 0);
     PARAM_LD : in std_logic;
     STOP : out std_logic;
@@ -62,11 +62,11 @@ architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_13_ip_wrapper is
 		ND_13IP_18_Exist : in std_logic;
 		ND_13IP_18_CLK : out std_logic;
 		ND_13IP_18_CTRL : in std_logic;
-		ND_13OP_1_d1_ND_13OP_1_Wr : out std_logic;
-		ND_13OP_1_d1_ND_13OP_1_Dout : out std_logic_vector(63 downto 0);
-		ND_13OP_1_d1_ND_13OP_1_Full : in std_logic;
-		ND_13OP_1_d1_ND_13OP_1_CLK : out std_logic;
-		ND_13OP_1_d1_ND_13OP_1_CTRL : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_Wr : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_Dout : out std_logic_vector(63 downto 0);
+		ND_13OP_1_ND_13OP_1_d1_Full : in std_logic;
+		ND_13OP_1_ND_13OP_1_d1_CLK : out std_logic;
+		ND_13OP_1_ND_13OP_1_d1_CTRL : out std_logic;
 		PARAM_DT : in std_logic_vector(10 downto 0);
 		PARAM_LD : in std_logic;
 		STOP : out std_logic;
@@ -98,11 +98,11 @@ bunny_static_split2rtl_hwn_nd_13_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_1
 		ND_13IP_18_Exist => ND_13IP_18_Exist,
 		ND_13IP_18_CLK => ND_13IP_18_CLK,
 		ND_13IP_18_CTRL => ND_13IP_18_CTRL,
-		ND_13OP_1_d1_ND_13OP_1_Wr => ND_13OP_1_d1_ND_13OP_1_Wr,
-		ND_13OP_1_d1_ND_13OP_1_Dout => ND_13OP_1_d1_ND_13OP_1_Dout,
-		ND_13OP_1_d1_ND_13OP_1_Full => ND_13OP_1_d1_ND_13OP_1_Full,
-		ND_13OP_1_d1_ND_13OP_1_CLK => ND_13OP_1_d1_ND_13OP_1_CLK,
-		ND_13OP_1_d1_ND_13OP_1_CTRL => ND_13OP_1_d1_ND_13OP_1_CTRL,
+		ND_13OP_1_ND_13OP_1_d1_Wr => ND_13OP_1_ND_13OP_1_d1_Wr,
+		ND_13OP_1_ND_13OP_1_d1_Dout => ND_13OP_1_ND_13OP_1_d1_Dout,
+		ND_13OP_1_ND_13OP_1_d1_Full => ND_13OP_1_ND_13OP_1_d1_Full,
+		ND_13OP_1_ND_13OP_1_d1_CLK => ND_13OP_1_ND_13OP_1_d1_CLK,
+		ND_13OP_1_ND_13OP_1_d1_CTRL => ND_13OP_1_ND_13OP_1_d1_CTRL,
 		PARAM_DT => PARAM_DT,
 		PARAM_LD => PARAM_LD,
 		STOP => STOP,

applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_hwn_nd_14_ip_wrapper.vhd

@@ -14,11 +14,11 @@ use compaandesign_com_bunny_static_split2rtl_hwn_nd_14_1_lib.all;
 
 entity bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
   port (
-    ND_14IP_20_ND_14IP_19_Rd : out std_logic;
-    ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
-    ND_14IP_20_ND_14IP_19_Exist : in std_logic;
-    ND_14IP_20_ND_14IP_19_CLK : out std_logic;
-    ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+    ND_14IP_19_ND_14IP_20_Rd : out std_logic;
+    ND_14IP_19_ND_14IP_20_Din : in std_logic_vector(63 downto 0);
+    ND_14IP_19_ND_14IP_20_Exist : in std_logic;
+    ND_14IP_19_ND_14IP_20_CLK : out std_logic;
+    ND_14IP_19_ND_14IP_20_CTRL : in std_logic;
     ND_14IP_21_Rd : out std_logic;
     ND_14IP_21_Din : in std_logic_vector(63 downto 0);
     ND_14IP_21_Exist : in std_logic;
@@ -52,11 +52,11 @@ architecture STRUCTURE of bunny_static_split2rtl_hwn_nd_14_ip_wrapper is
 		STIM_DIR : STRING := "hwn_nd_14"
 	);
 	port (
-		ND_14IP_20_ND_14IP_19_Rd : out std_logic;
-		ND_14IP_20_ND_14IP_19_Din : in std_logic_vector(63 downto 0);
-		ND_14IP_20_ND_14IP_19_Exist : in std_logic;
-		ND_14IP_20_ND_14IP_19_CLK : out std_logic;
-		ND_14IP_20_ND_14IP_19_CTRL : in std_logic;
+		ND_14IP_19_ND_14IP_20_Rd : out std_logic;
+		ND_14IP_19_ND_14IP_20_Din : in std_logic_vector(63 downto 0);
+		ND_14IP_19_ND_14IP_20_Exist : in std_logic;
+		ND_14IP_19_ND_14IP_20_CLK : out std_logic;
+		ND_14IP_19_ND_14IP_20_CTRL : in std_logic;
 		ND_14IP_21_Rd : out std_logic;
 		ND_14IP_21_Din : in std_logic_vector(63 downto 0);
 		ND_14IP_21_Exist : in std_logic;
@@ -88,11 +88,11 @@ bunny_static_split2rtl_hwn_nd_14_ip_wrapper_ip : bunny_static_split2rtl_hwn_nd_1
 		STIM_DIR => "compaandesign_com/bunny_static_split2rtl/hwn_nd_14/tb/data/"
 	)
     port map (
-		ND_14IP_20_ND_14IP_19_Rd => ND_14IP_20_ND_14IP_19_Rd,
-		ND_14IP_20_ND_14IP_19_Din => ND_14IP_20_ND_14IP_19_Din,
-		ND_14IP_20_ND_14IP_19_Exist => ND_14IP_20_ND_14IP_19_Exist,
-		ND_14IP_20_ND_14IP_19_CLK => ND_14IP_20_ND_14IP_19_CLK,
-		ND_14IP_20_ND_14IP_19_CTRL => ND_14IP_20_ND_14IP_19_CTRL,
+		ND_14IP_19_ND_14IP_20_Rd => ND_14IP_19_ND_14IP_20_Rd,
+		ND_14IP_19_ND_14IP_20_Din => ND_14IP_19_ND_14IP_20_Din,
+		ND_14IP_19_ND_14IP_20_Exist => ND_14IP_19_ND_14IP_20_Exist,
+		ND_14IP_19_ND_14IP_20_CLK => ND_14IP_19_ND_14IP_20_CLK,
+		ND_14IP_19_ND_14IP_20_CTRL => ND_14IP_19_ND_14IP_20_CTRL,
 		ND_14IP_21_Rd => ND_14IP_21_Rd,
 		ND_14IP_21_Din => ND_14IP_21_Din,
 		ND_14IP_21_Exist => ND_14IP_21_Exist,

applications/compaan/libraries/bunny_static_split/src/vhdl/bunny_static_split2rtl_register_rf_ip_wrapper.vhd

@@ -20,10 +20,6 @@ entity bunny_static_split2rtl_register_rf_ip_wrapper is
     write_en : in std_logic;
     write_data : in std_logic_vector(31 downto 0);
     pci_clk : in std_logic;
-    commit_rf_read_data : in std_logic_vector(31 downto 0);
-    commit_rf_read_en : out std_logic;
-    commit_rf_write_en : out std_logic;
-    commit_rf_write_data : out std_logic_vector(31 downto 0);
     brightness_rf_read_data : in std_logic_vector(31 downto 0);
     brightness_rf_read_en : out std_logic;
     brightness_rf_write_en : out std_logic;
@@ -43,9 +39,8 @@ architecture STRUCTURE of bunny_static_split2rtl_register_rf_ip_wrapper is
 
   component register_rf is
 	generic (
-		C_commit_rf_address : std_logic_vector := B"0000000000000000000";
-		C_brightness_rf_address : std_logic_vector := B"0000000000000000100";
-		C_count_rf_address : std_logic_vector := B"0000000000000001000"
+		C_brightness_rf_address : std_logic_vector := B"0000000000000000000";
+		C_count_rf_address : std_logic_vector := B"0000000000000000100"
 	);
 	port (
 		address : in std_logic_vector(18 downto 0);
@@ -54,10 +49,6 @@ architecture STRUCTURE of bunny_static_split2rtl_register_rf_ip_wrapper is
 		write_en : in std_logic;
 		write_data : in std_logic_vector(31 downto 0);
 		pci_clk : in std_logic;
-		commit_rf_read_data : in std_logic_vector(31 downto 0);
-		commit_rf_read_en : out std_logic;
-		commit_rf_write_en : out std_logic;
-		commit_rf_write_data : out std_logic_vector(31 downto 0);
 		brightness_rf_read_data : in std_logic_vector(31 downto 0);
 		brightness_rf_read_en : out std_logic;
 		brightness_rf_write_en : out std_logic;
@@ -75,9 +66,8 @@ begin
 
 bunny_static_split2rtl_register_rf_ip_wrapper_ip : register_rf
 	generic map (
-		C_commit_rf_address => B"0000000000000000000",
-		C_brightness_rf_address => B"0000000000000000100",
-		C_count_rf_address => B"0000000000000001000"
+		C_brightness_rf_address => B"0000000000000000000",
+		C_count_rf_address => B"0000000000000000100"
 	)
     port map (
 		address => address,
@@ -86,10 +76,6 @@ bunny_static_split2rtl_register_rf_ip_wrapper_ip : register_rf
 		write_en => write_en,
 		write_data => write_data,
 		pci_clk => pci_clk,
-		commit_rf_read_data => commit_rf_read_data,
-		commit_rf_read_en => commit_rf_read_en,
-		commit_rf_write_en => commit_rf_write_en,
-		commit_rf_write_data => commit_rf_write_data,
 		brightness_rf_read_data => brightness_rf_read_data,
 		brightness_rf_read_en => brightness_rf_read_en,
 		brightness_rf_write_en => brightness_rf_write_en,