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Commit 2b13fea1 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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Revert "Merge branch 'master' of git.astron.nl:desp/hdl" 

This reverts commit 37dfdaea
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Pipeline #26753 failed
Stage: simulation
Stage: synthesis
Stage: hardware
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applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+ 4
− 14
View file @ 2b13fea1
......@@ -29,13 +29,12 @@
-- .
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE ring_lib.ring_pkg.ALL;
USE work.sdp_pkg.ALL;
ENTITY node_sdp_beamformer IS
......@@ -86,9 +85,8 @@ ENTITY node_sdp_beamformer IS
reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo;
reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
ring_info : IN t_ring_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
-- beamlet data output
bdo_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
......@@ -130,13 +128,7 @@ ARCHITECTURE str OF node_sdp_beamformer IS
SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL beamlet_scale : STD_LOGIC_VECTOR(c_sdp_W_beamlet_scale-1 DOWNTO 0);
SIGNAL rn_index : NATURAL RANGE 0 TO c_sdp_N_pn_max-1 := 0;
BEGIN
rn_index <= TO_UINT(SUB_UVEC(gn_id, ring_info.O_rn)) WHEN rising_edge(dp_clk); -- Using register to ease timing closure.
---------------------------------------------------------------
-- Beamlet Subband Select
---------------------------------------------------------------
......@@ -191,8 +183,7 @@ BEGIN
dp_clk => dp_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
rn_index => rn_index,
local_bf_sosi => local_bf_sosi,
from_ri_sosi => from_ri_sosi,
to_ri_sosi => to_ri_sosi,
......@@ -381,7 +372,6 @@ BEGIN
ip_src_addr => stat_ip_src_addr,
gn_index => TO_UINT(gn_id),
ring_info => ring_info,
sdp_info => sdp_info,
weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
);
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+ 6
− 10
View file @ 2b13fea1
......@@ -41,8 +41,6 @@ ENTITY sdp_beamformer_remote IS
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
rn_index : IN NATURAL RANGE 0 TO c_sdp_N_pn_max-1 := 0;
local_bf_sosi : IN t_dp_sosi;
from_ri_sosi : IN t_dp_sosi;
to_ri_sosi : OUT t_dp_sosi;
......@@ -164,8 +162,6 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
node_index => rn_index,
-- Streaming input
in_sosi_arr => dispatch_sosi_arr,
out_sosi_arr => beamlets_data_sosi_arr
......@@ -176,10 +172,10 @@ BEGIN
BEGIN
beamlets_sosi_arr(0) <= beamlets_data_sosi_arr(0);
beamlets_sosi_arr(1) <= beamlets_data_sosi_arr(1);
beamlets_sosi_arr(0).re <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0));
beamlets_sosi_arr(0).im <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(0).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum));
beamlets_sosi_arr(1).re <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(1).data(c_sdp_W_beamlet_sum -1 DOWNTO 0));
beamlets_sosi_arr(1).im <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(1).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum));
beamlets_sosi_arr(0).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0);
beamlets_sosi_arr(0).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(0).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum);
beamlets_sosi_arr(1).re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data(c_sdp_W_beamlet_sum -1 DOWNTO 0);
beamlets_sosi_arr(1).im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= beamlets_data_sosi_arr(1).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum);
END PROCESS;
---------------------------------------------------------------
......@@ -222,8 +218,8 @@ BEGIN
bf_sum_sosi <= pipelined_beamlets_sosi; -- To preserve sosi control signals as dp_complex_add removes them.
bf_sum_data_sosi.data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
bf_sum_data_sosi.data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum) <= i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
bf_sum_sosi.re <= RESIZE_DP_DSP_DATA(i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0));
bf_sum_sosi.im <= RESIZE_DP_DSP_DATA(i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0));
bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0) <= i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
END PROCESS;
u_dp_repack_data_local : ENTITY dp_lib.dp_repack_data
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+ 4
− 5
View file @ 2b13fea1
......@@ -492,10 +492,10 @@ ARCHITECTURE str OF sdp_station IS
SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); -- weighted subbands
SIGNAL bs_sosi : t_dp_sosi;
SIGNAL xst_from_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL xst_to_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_from_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL bf_to_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL xst_from_ri_sosi : t_dp_sosi;
SIGNAL xst_to_ri_sosi : t_dp_sosi;
SIGNAL bf_from_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL bf_to_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0);
SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
......@@ -821,7 +821,6 @@ BEGIN
reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
sdp_info => sdp_info,
ring_info => ring_info,
gn_id => gn_id,
bdo_eth_src_mac => cep_eth_src_mac,
......
libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+ 8
− 8
View file @ 2b13fea1
......@@ -118,7 +118,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
TYPE t_bsn_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
TYPE t_channel_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_channel_w-1 DOWNTO 0);
TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
TYPE t_filled_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_buffer_nof_blocks-1 DOWNTO 0);
-- State
......@@ -136,7 +136,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
dp_sosi : t_dp_sosi;
-- p_read
rd_blk_pointer : INTEGER; -- use integer to detect need to wrap to natural
rd_offset : STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
rd_offset : STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
rd_copi : t_mem_copi;
fill_cipo_arr : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
out_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0); -- hold BSN until next sop, for easy view in Wave window
......@@ -251,7 +251,7 @@ BEGIN
-- p_write
IF in_sosi_arr_p(I).valid = '1' THEN
-- . increment address during block
v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(INCR_UVEC(r.wr_copi_arr(I).address(c_ram_buf.adr_w-1 DOWNTO 0), 1));
v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(INCR_UVEC(r.wr_copi_arr(I).address(c_mem_ram.adr_w-1 DOWNTO 0), 1));
v.wr_copi_arr(I).wr := '1';
v.wr_copi_arr(I).wrdata := RESIZE_MEM_SDATA(in_sosi_arr_p(I).data);
END IF;
......@@ -260,8 +260,8 @@ BEGIN
-- . set address at start of block
w.blk_pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0);
w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
-- . resize to c_ram_buf.adr_w
v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(RESIZE_UVEC(w.product_slv, c_ram_buf.adr_w));
-- . resize to c_mem_ram.adr_w
v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w));
-- . set filled flag at sop, so assume rest of block will follow in time
v.filled_arr(I)(TO_UINT(w.blk_pointer_slv)) := '1';
......@@ -292,7 +292,7 @@ BEGIN
-- . update read address of read block pointer
w.blk_pointer_slv := TO_UVEC(v.rd_blk_pointer, c_blk_pointer_w);
w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
v.rd_offset := RESIZE_UVEC(w.product_slv, c_ram_buf.adr_w);
v.rd_offset := RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w);
-- . issue mm_sosi, if there is output ready to be read, indicated by filled reference block
IF r.filled_arr(0)(v.rd_blk_pointer) = '1' THEN
......@@ -343,7 +343,7 @@ BEGIN
-- Do the output via the MM interface
--------------------------------------------------------------------------
-- . adjust the rd address to the current buffer output block
-- sum yields c_ram_buf.adr_w bits, because left operand in ADD_UVECdetermines width
-- sum yields c_mem_ram.adr_w bits, because left operand in ADD_UVECdetermines width
v.rd_copi := mm_copi;
v.rd_copi.address := RESIZE_MEM_ADDRESS(ADD_UVEC(r.rd_offset, mm_copi.address));
......@@ -357,7 +357,7 @@ BEGIN
-- Do the output via the DP streaming interface
--------------------------------------------------------------------------
-- . adjust the rd address
-- sum yields c_ram_buf.adr_w bits, because left operand in ADD_UVECdetermines width
-- sum yields c_mem_ram.adr_w bits, because left operand in ADD_UVECdetermines width
v.rd_copi := dp_copi;
v.rd_copi.address := RESIZE_MEM_ADDRESS(ADD_UVEC(r.rd_offset, dp_copi.address));
......
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