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Commit 2ad2defb authored by Reinier van der Walle's avatar Reinier van der Walle
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1 merge request!144Resolve L2SDP-425
...@@ -112,7 +112,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS ...@@ -112,7 +112,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one IS
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG"; CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST"; CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO"; CONSTANT c_mm_file_reg_crosslets_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_CROSSLETS_INFO";
CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB"; CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ"; CONSTANT c_mm_file_ram_st_xsq : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_XSQ";
-- Tb -- Tb
...@@ -286,10 +286,10 @@ BEGIN ...@@ -286,10 +286,10 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1 mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
-- bsn_scheduler_xsub -- bsn_scheduler_xsub
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1 mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- enable mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
-- Wait for enough WG data and start of sync interval -- Wait for enough WG data and start of sync interval
......
...@@ -79,7 +79,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS ...@@ -79,7 +79,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload IS
-- MM -- MM
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2"; CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST"; CONSTANT c_mm_file_reg_stat_enable_xst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_XST";
CONSTANT c_mm_file_reg_bsn_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB"; CONSTANT c_mm_file_reg_bsn_sync_scheduler_xsub : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SYNC_SCHEDULER_XSUB";
-- Tb -- Tb
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0';
...@@ -219,10 +219,10 @@ BEGIN ...@@ -219,10 +219,10 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Enable xsub -- Enable xsub
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 1, c_ctrl_interval_size, tb_clk); -- Interval size
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 2, 1, tb_clk); -- first write low then high part mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 2, 1, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1 mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 3, 0, tb_clk); -- assume v_bsn < 2**31-1
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_xsub, 0, 1, tb_clk); -- enable mmf_mm_bus_wr(c_mm_file_reg_bsn_sync_scheduler_xsub, 0, 1, tb_clk); -- enable
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
-- Offload enable -- Offload enable
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
......
...@@ -42,7 +42,7 @@ USE work.sdp_pkg.ALL; ...@@ -42,7 +42,7 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_crosslets_subband_select IS ENTITY sdp_crosslets_subband_select IS
GENERIC ( GENERIC (
g_N_crosslets : NATURAL := c_sdp_N_crosslets; g_N_crosslets : NATURAL := c_sdp_N_crosslets;
g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_clk_per_sync_min
); );
PORT ( PORT (
dp_clk : IN STD_LOGIC; dp_clk : IN STD_LOGIC;
......
...@@ -325,8 +325,7 @@ PACKAGE sdp_pkg is ...@@ -325,8 +325,7 @@ PACKAGE sdp_pkg is
init_sl => '0'); init_sl => '0');
CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w; CONSTANT c_sdp_crosslets_info_reg_w : NATURAL := c_sdp_mm_reg_crosslets_info.nof_dat*c_sdp_mm_reg_crosslets_info.dat_w;
CONSTANT c_sdp_xst_nof_blk_per_sync_max : NATURAL := 200000; CONSTANT c_sdp_xst_nof_clk_per_sync_min : NATURAL := (c_sdp_f_adc_MHz *10**6) / 10; -- 0.1 second
CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
-- XSUB MM address widths -- XSUB MM address widths
CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w; CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
......
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