Weekly commit

applications/lofar2/doc/prestudy/desp_hdl_design_article.txt

@@ -24,10 +24,12 @@ Idea / rule: Distinguish beteen state registers and pipeline registers.
   from output to input. If the component does use flow control than it can combinatorially impose this
   on the incomming flow control and pass the combined flow control on to its input. For timing closure
   the pipelining is added as a seperate stage. Either pipeline sosi if no flow control is needed
-  or pipeline siso if flow control is needed. For example: dp_block_resize.vhd, dp_counter.vhd.
+  or pipeline siso if flow control is needed. For example: dp_block_resize.vhd, dp_block_select.vhd,
+  dp_counter.vhd.
 
 
+$RADIOHDL_WORK/applications/lofar2/doc/prestudy/
 
 Ref:
  $RADIOHDL/tools/oneclick/doc/desp_firmware_dag_erko.txt
- $RADIOHDL/tools/oneclick/doc/desp_firmware_overview.txt
+ $RADIOHDL/tools/oneclick/doc/desp_firmware_overview.txt
\ No newline at end of file

applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt

@@ -98,27 +98,35 @@ Design decisions:
 
 
 *******************************************************************************
-* dp_validate_crc (dp_store_and_forward)
-* - Validate (geldig verklaren) CRC and store-and-forward or store-and-discard this packet
+* Possible names, choose names marked by +:
+* + dp_block_remove_channel --> pass on or remove block based on channel field at sop
+* + dp_block_remove_err --> pass on or remove block based on err field at eop
+* + dp_block_validate_bsn_at_sync --> pass on or remove all blocks in a sync interface based on bsn field at sync
+*   . validate = geldig verklaren
+*   . requires store and forward or store and discard of block
+* - dp_block_remove --> based on channel field at sop
+* - dp_block_filter_at_sop --> pass on or remove block based on channel field at sop
+* - dp_block_filter_at_eop --> pass on or remove block based on err field at eop
+* - dp_block_store_and_forward --> based on err field at eop
 *******************************************************************************
 
 The Ethernet/DP packet has two CRC checksums in the packet tail:
 
-- the Ethernet CRC is calculated by the 1GbE MAC and reported via the sosi.err field
-- the DP packet CRC is calculated by the dp_packet_dec.
+- the Ethernet CRC is calculated by the GbE MAC and reported via the sosi.err field
+- the DP packet CRC is calculated by the dp_packet_dec and reported via the sosi.err field
 
-The CRC information is in the packet tail. Therefore the packet needs to be stored, before it can
-be validated, because the entire packet is needed to calculate and verify the CRC. Dependent on
-the validation outcome the packet is either forwared or discarded. The CRC results are reported
-via the sosi.err field at the end of packet (eop). The dp_validate_crc forwards the packet when
-the sosi.err CRC is correct and discards the packet when the CRC is wrong.
+The CRC results are reported via the sosi.err field at the end of packet (eop).
 
-The dp_validate_crc uses dp_store_and_forward. The decision is known when the eop is received and
-must then be applied at the sop, to either release the block or discard it.
+The sosi.err field information is valid at sosi.eop of the block, so at the end of the block.
+Therefore the packet needs to be stored, before it can be validated. Dependent on
+the validation outcome the packet is either forwared or discarded. The dp_block_store_and_forward
+forwards the block when the sosi.err = 0 and else it discards the block.
 
-- Rx ETH MAC puts ETH CRC result in sosi.err at eop
-- Rx DP decode puts DP CRC result in sosi.err at eop
-- dp_validate_crc stores the packet and forwards if it has no error at the eop
+The decision is known when the eop is received and must then be applied at the sop, to either
+release the block or discard it.
+
+- When g_validate_crc = TRUE then dp_block_store_and_forward stores the packet and only forwards
+  if it has no error at the eop, else it 
 
 
 

applications/lofar2/doc/prestudy/station2_sdp_ring.txt

@@ -5,6 +5,19 @@ Detailed design: RING
 * Ring links:
 *******************************************************************************
 
+10GBE end of frame:
+avalon_st_rx_error[5:0] valid at eop
+his signal indicates one or more errors in the currentpacket being transferred on the Avalon streaming RXinterface. It is qualified by the avalon_st_rx_valid andavalon_st_rx_ready signals and aligned to the end ofpacket.
+• Bit 0—PHY error.
+  —For 10 Gbps, the data on xgmii_rx_data contains acontrol error character (FE).
+  —For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err ormii_rx_err is asserted.
+  —For 1G/2.5G, gmii16b_rx_err is asserted.
+• Bit 1—CRC error. The computed CRC value does notmatch the CRC received.
+• Bit 2—Undersized frame. The RX frame length is less than 64 bytes.
+• Bit 3—Oversized frame.
+• Bit 4—Payload length error.
+• Bit 5—Overflow error. The user application is not readyto receive more data while still receiving incoming datafrom the MAC IP core.
+
 DONE: 
 Ring latency:
 The RSP boards use wormhole routing on the ring. The latency of 1 hop between RSP boards is about