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Commit 29510d26 authored by Eric Kooistra's avatar Eric Kooistra
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Added rx_cnt_arr to MM reg.

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libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+ 32
− 18
View file @ 29510d26
......@@ -33,6 +33,12 @@
-- |-----------------------------------------------------------------------|
-- | res_val_n = [1], res_ok_n = [0] | 1
-- |-----------------------------------------------------------------------|
-- | rx_cnt[31:0] | 2
-- |-----------------------------------------------------------------------|
--
-- . g_nof_streams
-- The MM control register for stream I in 0:g_nof_streams-1 starts at word
-- index wi = I * 2**c_mm_reg.adr_w.
--
-- . Results
-- When res_val_n = '1' then no valid data is being received. When
......@@ -53,7 +59,11 @@
-- CNTR or LFSR data for the DP data. If the higher bits do notmatch the
-- sequence in the lower bits, then the rx data is forced to -1, and that
-- will then be detected and reported by u_diag_rx_seq as a sequence error.
--
-- . rx_cnt
-- Counts the number of valid input data that was received since diag_en
-- went active. An incrementing rx_cnt shows that data is being received.
--
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
......@@ -89,38 +99,39 @@ ARCHITECTURE str OF mms_diag_rx_seq IS
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => 1,
adr_w => 2,
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 2,
nof_dat => 3,
init_sl => '0');
CONSTANT c_reg_slv_w : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
TYPE t_reg_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_reg_slv_w-1 DOWNTO 0);
TYPE t_seq_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
TYPE t_reg_slv_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_reg_slv_w-1 DOWNTO 0);
TYPE t_seq_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
TYPE t_data_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
SIGNAL reg_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL reg_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
-- Registers in dp_clk domain
SIGNAL ctrl_reg_arr : t_reg_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
SIGNAL stat_reg_arr : t_reg_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
SIGNAL ctrl_reg_arr : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
SIGNAL stat_reg_arr : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
SIGNAL diag_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_sel_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_seq_arr : t_seq_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
SIGNAL rx_seq_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_seq_val_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_data_arr : t_data_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_data_val_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_res_arr : t_seq_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_res_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL diag_res_val_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL stat_res_ok_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL stat_res_val_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL reg_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL reg_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
ASSERT g_data_w >= g_seq_dat_w REPORT "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." SEVERITY FAILURE;
......@@ -156,6 +167,7 @@ BEGIN
-- detect rx sequence errors
u_diag_rx_seq: ENTITY WORK.diag_rx_seq
GENERIC MAP (
g_cnt_w => c_word_w,
g_dat_w => g_seq_dat_w,
g_diag_res_w => g_seq_dat_w -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
)
......@@ -172,6 +184,7 @@ BEGIN
diag_res_val => diag_res_val_arr(I),
-- Streaming
in_cnt => rx_cnt_arr(I),
in_dat => rx_seq_arr(I),
in_val => rx_seq_val_arr(I)
);
......@@ -186,19 +199,20 @@ BEGIN
diag_sel_arr(I) <= ctrl_reg_arr(I)(1); -- address 0, data bit [1]
-- address 1, not used for control
-- . read stat_reg_arr
p_stat_reg_arr : PROCESS(ctrl_reg_arr, stat_res_ok_n_arr, stat_res_val_n_arr)
p_stat_reg_arr : PROCESS(ctrl_reg_arr, stat_res_ok_n_arr, stat_res_val_n_arr, rx_cnt_arr)
BEGIN
-- Default write / readback:
stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0, control read back
stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0: control read back
-- Status read only:
stat_reg_arr(I)(0+c_word_w) <= stat_res_ok_n_arr(I); -- address 1, data bit [0]
stat_reg_arr(I)(1+c_word_w) <= stat_res_val_n_arr(I); -- address 1, data bit [1]
stat_reg_arr(I)( 0+1*c_word_w) <= stat_res_ok_n_arr(I); -- address 1, data bit [0]
stat_reg_arr(I)( 1+1*c_word_w) <= stat_res_val_n_arr(I); -- address 1, data bit [1]
stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= rx_cnt_arr(I); -- address 2: read rx_cnt per stream
END PROCESS;
u_reg : ENTITY common_lib.common_reg_r_w_dc
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_readback => FALSE, -- using FALSE fits for write/read or read only register
g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
g_reg => c_mm_reg
)
PORT MAP (
......
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