-Created subtypes COPI/CIPO in common_mem_pkg;

-Renamed MOSI/MISO in (tb_)mms_st_histogram;
-Renamed (tb)_mms_* to (tb)_mmp_*;
-Recompiled and reverified in simulation: all OK.

libraries/base/common/src/vhdl/common_mem_pkg.vhd

@@ -60,19 +60,19 @@ PACKAGE common_mem_pkg IS
   CONSTANT c_mem_address_sz : NATURAL := c_mem_address_w/c_byte_w;
   CONSTANT c_mem_data_sz    : NATURAL := c_mem_data_w/c_byte_w;
   
-  TYPE t_mem_miso IS RECORD  -- Master In Slave Out
+  TYPE t_mem_miso IS RECORD  -- Master In Slave Out. For backward compatibility only. Use t_mem_copi for new designs.
     rddata      : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);  -- data width (suits 1, 2 or 4 bytes)
     rdval       : STD_LOGIC;
     waitrequest : STD_LOGIC;
   END RECORD;
   
-  TYPE t_mem_mosi IS RECORD  -- Master Out Slave In
+  TYPE t_mem_mosi IS RECORD  -- Master Out Slave In.  For backward compatibility only. Use t_mem_cipo for new designs.
     address     : STD_LOGIC_VECTOR(c_mem_address_w-1 DOWNTO 0);  -- address range (suits 32-bit processor)
     wrdata      : STD_LOGIC_VECTOR(c_mem_data_w-1 DOWNTO 0);     -- data width (suits 1, 2 or 4 bytes)
     wr          : STD_LOGIC;
     rd          : STD_LOGIC;
   END RECORD;
-  
+ 
   CONSTANT c_mem_miso_rst : t_mem_miso := ((OTHERS=>'0'), '0', '0');
   CONSTANT c_mem_mosi_rst : t_mem_mosi := ((OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
   
@@ -94,7 +94,17 @@ PACKAGE common_mem_pkg IS
   FUNCTION RESIZE_MEM_UDATA(  vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;  -- unsigned
   FUNCTION RESIZE_MEM_SDATA(  vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;  -- sign extended
   FUNCTION RESIZE_MEM_XDATA(  vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;  -- set unused MSBits to 'X'
-  
+
+  -- MOSI/MISO subtypes  
+  SUBTYPE t_mem_copi IS t_mem_mosi; -- Controller Out Peripheral In
+  SUBTYPE t_mem_cipo IS t_mem_miso; -- Peripheral In Controller Out
+
+  CONSTANT c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
+  CONSTANT c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
+
+  SUBTYPE t_mem_cipo_arr IS t_mem_miso_arr;
+  SUBTYPE t_mem_copi_arr IS t_mem_mosi_arr;
+ 
   
   ------------------------------------------------------------------------------
   -- Burst memory access (for DDR access interface)

libraries/dsp/st/hdllib.cfg

@@ -16,7 +16,7 @@ synth_files =
     src/vhdl/st_xst.vhd 
 #    src/vhdl/st_top.vhd 
     src/vhdl/st_histogram.vhd
-    src/vhdl/mms_st_histogram.vhd
+    src/vhdl/mmp_st_histogram.vhd
 
     tb/vhdl/tb_st_pkg.vhd 
  
@@ -30,7 +30,7 @@ test_bench_files =
     tb/vhdl/tb_tb_st_xst.vhd
     tb/vhdl/tb_st_histogram.vhd
 
-    tb/vhdl/tb_mms_st_histogram.vhd
+    tb/vhdl/tb_mmp_st_histogram.vhd
     tb/vhdl/tb_st_histogram.vhd
     tb/vhdl/tb_tb_st_histogram.vhd
 

libraries/dsp/st/src/vhdl/mms_st_histogram.vhd → libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd

@@ -34,7 +34,7 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
-ENTITY mms_st_histogram IS
+ENTITY mmp_st_histogram IS
   GENERIC (
     g_nof_instances     : NATURAL;
     g_data_w            : NATURAL;
@@ -50,12 +50,12 @@ ENTITY mms_st_histogram IS
     mm_clk     : IN  STD_LOGIC;
     mm_rst     : IN  STD_LOGIC;               
 
-    ram_mosi   : IN  t_mem_mosi;
-    ram_miso   : OUT t_mem_miso
+    ram_copi   : IN  t_mem_copi;
+    ram_cipo   : OUT t_mem_cipo
   );
-END mms_st_histogram;
+END mmp_st_histogram;
 
-ARCHITECTURE str OF mms_st_histogram IS
+ARCHITECTURE str OF mmp_st_histogram IS
 
   CONSTANT c_reg_adr_w : NATURAL := 1;
   CONSTANT c_ram_adr_w : NATURAL := ceil_log2(g_nof_bins);
@@ -69,16 +69,16 @@ ARCHITECTURE str OF mms_st_histogram IS
 
   CONSTANT c_addr_high : NATURAL := g_nof_bins-1;
 
-  SIGNAL common_ram_cr_cw_wr_mosi_arr : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL common_ram_cr_cw_wr_copi_arr : t_mem_copi_arr(g_nof_instances-1 DOWNTO 0);
 
-  SIGNAL common_ram_cr_cw_rd_mosi_arr : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
-  SIGNAL common_ram_cr_cw_rd_miso_arr : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0); 
+  SIGNAL common_ram_cr_cw_rd_copi_arr : t_mem_copi_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL common_ram_cr_cw_rd_cipo_arr : t_mem_cipo_arr(g_nof_instances-1 DOWNTO 0); 
 
-  SIGNAL st_histogram_ram_mosi_arr  : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
-  SIGNAL st_histogram_ram_miso_arr  : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL st_histogram_ram_copi_arr  : t_mem_copi_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL st_histogram_ram_cipo_arr  : t_mem_cipo_arr(g_nof_instances-1 DOWNTO 0);
 
-  SIGNAL ram_mosi_arr  : t_mem_mosi_arr(g_nof_instances-1 DOWNTO 0);
-  SIGNAL ram_miso_arr  : t_mem_miso_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL ram_copi_arr  : t_mem_copi_arr(g_nof_instances-1 DOWNTO 0);
+  SIGNAL ram_cipo_arr  : t_mem_cipo_arr(g_nof_instances-1 DOWNTO 0);
 
   SIGNAL ram_fill_arr  : STD_LOGIC_VECTOR(g_nof_instances-1 DOWNTO 0);
 
@@ -109,8 +109,8 @@ BEGIN
       
       snk_in       => snk_in_arr(i),
   
-      ram_mosi     => st_histogram_ram_mosi_arr(i),
-      ram_miso     => st_histogram_ram_miso_arr(i)
+      ram_mosi     => st_histogram_ram_copi_arr(i),
+      ram_miso     => st_histogram_ram_cipo_arr(i)
     );
   END GENERATE;
 
@@ -130,22 +130,22 @@ BEGIN
       wr_clk   => dp_clk,
       wr_rst   => dp_rst, 
       wr_clken => '1',
-      wr_en    => common_ram_cr_cw_wr_mosi_arr(i).wr,
-      wr_adr   => common_ram_cr_cw_wr_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
-      wr_dat   => common_ram_cr_cw_wr_mosi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0),
+      wr_en    => common_ram_cr_cw_wr_copi_arr(i).wr,
+      wr_adr   => common_ram_cr_cw_wr_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+      wr_dat   => common_ram_cr_cw_wr_copi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0),
       rd_clk   => mm_clk,
       rd_rst   => mm_rst, 
       rd_clken => '1',
-      rd_en    => common_ram_cr_cw_rd_mosi_arr(i).rd,
-      rd_adr   => common_ram_cr_cw_rd_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
-      rd_dat   => common_ram_cr_cw_rd_miso_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0),
-      rd_val   => common_ram_cr_cw_rd_miso_arr(i).rdval
+      rd_en    => common_ram_cr_cw_rd_copi_arr(i).rd,
+      rd_adr   => common_ram_cr_cw_rd_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+      rd_dat   => common_ram_cr_cw_rd_cipo_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0),
+      rd_val   => common_ram_cr_cw_rd_cipo_arr(i).rdval
     );
   END GENERATE;
  
   -- User side MM bus for histogram readout
-  common_ram_cr_cw_rd_mosi_arr <= ram_mosi_arr;
-  ram_miso_arr <= common_ram_cr_cw_rd_miso_arr;
+  common_ram_cr_cw_rd_copi_arr <= ram_copi_arr;
+  ram_cipo_arr <= common_ram_cr_cw_rd_cipo_arr;
 
 
   -------------------------------------------------------------------------------
@@ -159,19 +159,19 @@ BEGIN
   nxt_ram_filling <= '0' WHEN TO_UINT(address)=c_addr_high ELSE '1' WHEN ram_fill='1' ELSE ram_filling;
   nxt_address <= (OTHERS=>'0') WHEN ram_filling='0' ELSE INCR_UVEC(address, 1) WHEN ram_filling='1' ELSE address;
 
-  -- Do read request on ram_mosi when ram_filling
-  gen_mosi_arr: FOR i IN 0 TO g_nof_instances-1 GENERATE
-    st_histogram_ram_mosi_arr(i).wr                              <= '0';
-    st_histogram_ram_mosi_arr(i).wrdata                          <= (OTHERS=>'0');
-    st_histogram_ram_mosi_arr(i).rd                              <= ram_filling;
-    st_histogram_ram_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
+  -- Do read request on ram_copi when ram_filling
+  gen_copi_arr: FOR i IN 0 TO g_nof_instances-1 GENERATE
+    st_histogram_ram_copi_arr(i).wr                              <= '0';
+    st_histogram_ram_copi_arr(i).wrdata                          <= (OTHERS=>'0');
+    st_histogram_ram_copi_arr(i).rd                              <= ram_filling;
+    st_histogram_ram_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
   END GENERATE;
 
-  -- Forward the read histogram data from ram_miso into write mosi of dual clock RAM
-  gen_rd_miso_to_wr_mosi: FOR i IN 0 TO g_nof_instances-1 GENERATE
-    common_ram_cr_cw_wr_mosi_arr(i).wr                              <= st_histogram_ram_miso_arr(i).rdval;
-    common_ram_cr_cw_wr_mosi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0)  <= st_histogram_ram_miso_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0);
-    common_ram_cr_cw_wr_mosi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
+  -- Forward the read histogram data from ram_cipo into write copi of dual clock RAM
+  gen_rd_cipo_to_wr_copi: FOR i IN 0 TO g_nof_instances-1 GENERATE
+    common_ram_cr_cw_wr_copi_arr(i).wr                              <= st_histogram_ram_cipo_arr(i).rdval;
+    common_ram_cr_cw_wr_copi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0)  <= st_histogram_ram_cipo_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0);
+    common_ram_cr_cw_wr_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0) <= address;
   END GENERATE;
 
   -- Registers
@@ -195,10 +195,10 @@ BEGIN
     g_mult_addr_w => c_ram_adr_w
   )
   PORT MAP (
-    mosi     => ram_mosi,
-    miso     => ram_miso,
-    mosi_arr => ram_mosi_arr,
-    miso_arr => ram_miso_arr
+    mosi     => ram_copi,
+    miso     => ram_cipo,
+    mosi_arr => ram_copi_arr,
+    miso_arr => ram_cipo_arr
   );
 
 END str;

libraries/dsp/st/tb/vhdl/tb_mms_st_histogram.vhd → libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd

@@ -43,7 +43,7 @@ USE common_lib.tb_common_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE dp_lib.tb_dp_pkg.ALL;
 
-ENTITY tb_mms_st_histogram IS
+ENTITY tb_mmp_st_histogram IS
   GENERIC(
     g_nof_sync          : NATURAL := 4;
     g_nof_instances     : NATURAL := 12;
@@ -51,10 +51,10 @@ ENTITY tb_mms_st_histogram IS
     g_nof_bins          : NATURAL := 512;
     g_nof_data_per_sync : NATURAL := 32768 
   );
-END tb_mms_st_histogram;
+END tb_mmp_st_histogram;
 
 
-ARCHITECTURE tb OF tb_mms_st_histogram IS
+ARCHITECTURE tb OF tb_mmp_st_histogram IS
  
   ---------------------------------------------------------------------------
   -- Clocks and resets
@@ -83,8 +83,8 @@ ARCHITECTURE tb OF tb_mms_st_histogram IS
   ----------------------------------------------------------------------------
   SIGNAL st_histogram_snk_in_arr : t_dp_sosi_arr(g_nof_instances-1 DOWNTO 0);
 
-  SIGNAL st_histogram_ram_mosi   : t_mem_mosi;
-  SIGNAL st_histogram_ram_miso   : t_mem_miso;
+  SIGNAL st_histogram_ram_copi   : t_mem_copi;
+  SIGNAL st_histogram_ram_cipo   : t_mem_cipo;
 
    
   ----------------------------------------------------------------------------
@@ -137,14 +137,15 @@ BEGIN
     WAIT;
   END PROCESS;
 
+
   ----------------------------------------------------------------------------
-  -- mms_st_histogram
+  -- mmp_st_histogram
   ----------------------------------------------------------------------------
   gen_snk_in_arr: FOR i IN 0 TO g_nof_instances-1 GENERATE
     st_histogram_snk_in_arr(i) <= stimuli_src_out;
   END GENERATE;
 
-  u_mms_st_histogram : ENTITY work.mms_st_histogram
+  u_mmp_st_histogram : ENTITY work.mmp_st_histogram
   GENERIC MAP(
     g_nof_instances     => g_nof_instances,
     g_data_w            => g_data_w,
@@ -160,8 +161,8 @@ BEGIN
 
     snk_in_arr   => st_histogram_snk_in_arr,
 
-    ram_mosi     => st_histogram_ram_mosi,
-    ram_miso     => st_histogram_ram_miso
+    ram_copi     => st_histogram_ram_copi,
+    ram_cipo     => st_histogram_ram_cipo
   );
 
 
@@ -170,7 +171,7 @@ BEGIN
   ---------------------------------------------------------------------------- 
   p_ram_clear : PROCESS
   BEGIN
-    st_histogram_ram_mosi <= c_mem_mosi_rst;
+    st_histogram_ram_copi <= c_mem_copi_rst;
     ram_rd_word <= (OTHERS=>'0');
 
      -- The first sync indicates start of incoming data - let it pass
@@ -182,15 +183,15 @@ BEGIN
 
      -- Read out the RAM contents
      FOR k IN 0 TO g_nof_bins-1 LOOP
-       proc_mem_mm_bus_rd(k, mm_clk, st_histogram_ram_mosi);
-       ram_rd_word <= st_histogram_ram_miso.rddata(c_ram_dat_w-1 DOWNTO 0);
+       proc_mem_mm_bus_rd(k, mm_clk, st_histogram_ram_copi);
+       ram_rd_word <= st_histogram_ram_cipo.rddata(c_ram_dat_w-1 DOWNTO 0);
        ram_rd_word_int <= TO_UINT(ram_rd_word);
      END LOOP;
 
    END LOOP;
   END PROCESS;
 
-  -- Register st_histogram_ram_miso.rdval so we read only valid data
+  -- Register st_histogram_ram_cipo.rdval so we read only valid data
   p_nxt_ram_rd_word_valid : PROCESS(mm_rst, mm_clk)
   BEGIN
    IF mm_rst = '1' THEN
@@ -199,7 +200,7 @@ BEGIN
       ram_rd_word_valid <= nxt_ram_rd_word_valid;
     END IF;
   END PROCESS;
-  nxt_ram_rd_word_valid <= st_histogram_ram_miso.rdval;
+  nxt_ram_rd_word_valid <= st_histogram_ram_cipo.rdval;
 
 
   ----------------------------------------------------------------------------