instantiated st_histogram in node_adc_input_and_timing

applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg

 hdl_lib_name = lofar2_unb2b_adc
 hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b st
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd

@@ -26,7 +26,7 @@
 --   Contains all the signal processing blocks to receive and time the ADC input data
 --   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -141,6 +141,11 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
   CONSTANT c_data_w                 : NATURAL := 16;
   CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
   
+  -- Histogram
+  CONSTANT c_st_histogram_in_data_w : NATURAL := 14;
+  CONSTANT c_st_histogram_nof_bins  : NATURAL := 512;
+  CONSTANT c_st_histogram_str       : STRING  := "freq.density";
+ 
  
   -- QSFP leds
   SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -485,6 +490,34 @@ BEGIN
   );
   
   
+  -----------------------------------------------------------------------------
+  -- Histogram
+  -----------------------------------------------------------------------------
+  
+  u_st_histogram : ENTITY st_lib.st_histogram
+  GENERIC MAP (
+    g_in_data_w         => c_st_histogram_in_data_w, -- 14, -- c_data_w,
+    g_nof_bins          => c_st_histogram_nof_bins, -- 512,
+    g_nof_data          => c_lofar2_sample_clk_freq,
+    g_str               => c_st_histogram_str,
+    g_ram_miso_sim_mode => g_sim -- is the specific output data even allowed when this is TRUE ??
+  )
+  PORT MAP (
+    dp_rst              => rx_rst,
+    dp_clk              => rx_clk,
+                    
+    -- Streaming    
+    snk_in              => st_sosi_arr(0),
+    
+    -- DP clocked memory bus
+    sla_in_ram_mosi     => c_mem_mosi_rst,             -- Beware, works in dp clock domain !
+    sla_out_ram_miso    => OPEN,                       --  ''                              !
+    
+    -- Debug bus
+    dbg_ram_miso        => OPEN                        --  ''                              !
+  );
+
+
   -----------------------------------------------------------------------------
   -- Output Stage
   --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain