Use g_dp_factor>1 to verify c_rd_fifo_af_margin.

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -53,10 +53,10 @@ ENTITY tb_io_ddr IS
     g_ctlr_ref_clk_period   : TIME := 5000 ps;   -- 200 MHz
     g_dvr_clk_period        : TIME := 5000 ps;   -- 50 MHz
     g_dp_clk_period         : TIME := 5000 ps;   -- 200 MHz
-    g_dp_factor             : NATURAL := 1;      -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
-    g_rd_fifo_depth         : NATURAL := 256;    -- default 256 because 32b*256 fits in 1 M9K, use larger to fit more read bursts eg. in case g_dp_factor>1
+    g_dp_factor             : NATURAL := 4;      -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
+    g_rd_fifo_depth         : NATURAL := 512;    -- default 256 because 32b*256 fits in 1 M9K, use larger to fit more read bursts eg. in case g_dp_factor>1
     g_block_len             : NATURAL := 2500;   -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
-    g_nof_block             : NATURAL := 3;      -- number of blocks that will be written to DDR and readback from DDR
+    g_nof_block             : NATURAL := 2;      -- number of blocks that will be written to DDR and readback from DDR
     g_nof_wr_per_block      : NATURAL := 1;      -- number of write accesses per block
     g_nof_rd_per_block      : NATURAL := 1;      -- number of read accesses per block
     g_nof_repeat            : NATURAL := 1;      -- number of stimuli repeats with write flush after each repeat