Added support for g_nof_streams > 0

libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd

@@ -49,7 +49,7 @@ USE work.tb_dp_pkg.ALL;
 ENTITY tb_mms_dp_fifo_fill IS
   GENERIC (
     -- Try FIFO settings
-    g_nof_streams     : POSITIVE := 1;
+    g_nof_streams     : POSITIVE := 3;
     g_dut_use_bsn     : BOOLEAN  := FALSE;
     g_dut_use_empty   : BOOLEAN  := FALSE;
     g_dut_use_channel : BOOLEAN  := FALSE;
@@ -63,6 +63,11 @@ END tb_mms_dp_fifo_fill;
 
 ARCHITECTURE tb OF tb_mms_dp_fifo_fill IS
 
+  CONSTANT c_nof_regs_per_stream       : NATURAL := 3; 
+  CONSTANT c_reg_used_words_offset     : NATURAL := 0; 
+  CONSTANT c_reg_fifo_flags            : NATURAL := 1; 
+  CONSTANT c_reg_max_used_words_offset : NATURAL := 2; 
+  
   ----------------------------------------------------------------------------
   -- Clocks and resets
   ----------------------------------------------------------------------------   
@@ -88,6 +93,7 @@ ARCHITECTURE tb OF tb_mms_dp_fifo_fill IS
   SIGNAL reg_dp_fifo_fill_mosi : t_mem_mosi := c_mem_mosi_rst;  
   SIGNAL reg_dp_fifo_fill_miso : t_mem_miso := c_mem_miso_rst;  
 
+  SIGNAL in_sosi               : t_dp_sosi  := c_dp_sosi_rst;
   SIGNAL in_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=> c_dp_sosi_rst);
   SIGNAL out_siso_arr          : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL out_sosi_arr          : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
@@ -108,15 +114,15 @@ BEGIN
     proc_common_wait_some_cycles(dp_clk, 10);
     -- Generate a datastream. 
     WHILE TRUE LOOP
-      in_sosi_arr(0).valid <= '1';
-      in_sosi_arr(0).sop <= '1';                 
+      in_sosi.valid <= '1';
+      in_sosi.sop <= '1';                 
       proc_common_wait_some_cycles(dp_clk, 1);
-      in_sosi_arr(0).sop <= '0';
+      in_sosi.sop <= '0';
       proc_common_wait_some_cycles(dp_clk, 63);                 
-      in_sosi_arr(0).eop <= '1';                 
+      in_sosi.eop <= '1';                 
       proc_common_wait_some_cycles(dp_clk, 1);
-      in_sosi_arr(0).eop <= '0';
-      in_sosi_arr(0).valid <= '0';
+      in_sosi.eop <= '0';
+      in_sosi.valid <= '0';
       proc_common_wait_some_cycles(dp_clk, 1);  
       WHILE (sim_used_words = '0' AND sim_wr_full = '0') LOOP 
         proc_common_wait_some_cycles(dp_clk, 1);
@@ -124,26 +130,45 @@ BEGIN
     END LOOP; 
   END PROCESS;   
 
-  out_siso_arr(0) <= c_dp_siso_rdy WHEN sim_wr_full = '0' ELSE c_dp_siso_rst; 
+  gen_connect : FOR I IN 0 TO g_nof_streams-1 GENERATE 
+    in_sosi_arr(I)  <= in_sosi;
+    out_siso_arr(I) <= c_dp_siso_rdy WHEN sim_wr_full = '0' ELSE c_dp_siso_rst; 
+  END GENERATE; 
 
   p_special_stimuli : PROCESS
   BEGIN
     -- Read out the used_w register
     sim_used_words <= '1';
     proc_common_wait_some_cycles(mm_clk, 200);
-    proc_mem_mm_bus_rd(0, mm_clk, reg_dp_fifo_fill_mosi);   
+    FOR I IN 0 TO g_nof_streams-1 LOOP
+      proc_mem_mm_bus_rd(I*c_nof_regs_per_stream + c_reg_used_words_offset, mm_clk, reg_dp_fifo_fill_mosi);   
+    END LOOP;
     sim_used_words <= '0';
     
-    -- Read out the rd_empty bit 
+    -- Read maximum used fifo words register
     sim_rd_empty <= '1';
+    proc_common_wait_some_cycles(mm_clk, 30);
+    FOR I IN 0 TO g_nof_streams-1 LOOP
+      proc_mem_mm_bus_rd(I*c_nof_regs_per_stream + c_reg_max_used_words_offset, mm_clk, reg_dp_fifo_fill_mosi);   
+    END LOOP;
+
+--    proc_mem_mm_bus_rd(2, mm_clk, reg_dp_fifo_fill_mosi);   
+    
+    -- Read out the rd_empty bit 
     proc_common_wait_some_cycles(mm_clk, 100);
-    proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);   
+--    proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);   
+    FOR I IN 0 TO g_nof_streams-1 LOOP
+      proc_mem_mm_bus_rd(I*c_nof_regs_per_stream + c_reg_fifo_flags, mm_clk, reg_dp_fifo_fill_mosi);   
+    END LOOP;
     sim_rd_empty <= '0';
     
     -- Read out the wr_full bit 
     sim_wr_full <= '1';
     proc_common_wait_some_cycles(mm_clk, 100);
-    proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);   
+    FOR I IN 0 TO g_nof_streams-1 LOOP
+      proc_mem_mm_bus_rd(I*c_nof_regs_per_stream + c_reg_fifo_flags, mm_clk, reg_dp_fifo_fill_mosi);   
+    END LOOP;
+--    proc_mem_mm_bus_rd(1, mm_clk, reg_dp_fifo_fill_mosi);   
 
     proc_common_wait_some_cycles(mm_clk, 10);
     tb_end <= '1';