added mm interface for reconfiguration logic in the ip_arria_10_e3sge3_phy_10gbase_r_24 ip

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -99,6 +99,9 @@ ENTITY tr_10GbE IS
     mdio_mosi_arr       : IN  t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
     mdio_miso_arr       : OUT t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
+
     -- DP interface
     dp_rst              : IN  STD_LOGIC := '0';
     dp_clk              : IN  STD_LOGIC := '0';
@@ -264,6 +267,9 @@ BEGIN
     
     reg_eth10g_mosi  => reg_eth10g_mosi, -- ETH10G (link status register)
     reg_eth10g_miso  => reg_eth10g_miso,
+
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,      
       
     -- ST
     tx_snk_in_arr    => dp_fifo_fill_tx_src_out_arr,      -- 64 bit data @ 156 MHz

libraries/technology/10gbase_r/tech_10gbase_r.vhd

@@ -25,6 +25,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 
 ENTITY tech_10gbase_r IS
@@ -35,6 +36,12 @@ ENTITY tech_10gbase_r IS
     g_nof_channels   : NATURAL := 1
   );
   PORT (
+    -- MM
+    mm_clk            : IN  STD_LOGIC := '0';
+    mm_rst            : IN  STD_LOGIC := '0';
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
+
     -- Transceiver ATX PLL reference clock
     tr_ref_clk_644          : IN  STD_LOGIC;   -- 644.531250 MHz
     
@@ -74,7 +81,10 @@ BEGIN
   gen_ip_arria10_e3sge3 : IF c_use_technology=TRUE AND g_technology=c_tech_arria10_e3sge3 GENERATE
     u0 : ENTITY work.tech_10gbase_r_arria10_e3sge3
     GENERIC MAP (g_sim, g_nof_channels)
-    PORT MAP (tr_ref_clk_644,
+    PORT MAP (mm_clk, mm_rst,
+              reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+              reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,   
+              tr_ref_clk_644,
               clk_156, rst_156,
               xgmii_tx_ready_arr, xgmii_rx_ready_arr, xgmii_tx_dc_arr, xgmii_rx_dc_arr,
               tx_serial_arr, rx_serial_arr);

libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd

@@ -36,6 +36,7 @@ LIBRARY ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_cont
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 USE tech_pll_lib.tech_pll_component_pkg.ALL;
 USE work.tech_10gbase_r_component_pkg.ALL;
@@ -46,10 +47,16 @@ ENTITY tech_10gbase_r_arria10_e3sge3 IS
     g_nof_channels        : NATURAL := 1
   );
   PORT (
+    -- MM
+    mm_clk            : IN  STD_LOGIC := '0';
+    mm_rst            : IN  STD_LOGIC := '0';
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi:= c_mem_mosi_rst; 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
+
     -- Transceiver ATX PLL reference clock
     tr_ref_clk_644          : IN  STD_LOGIC;   -- 644.531250 MHz
     
-    -- XGMII clocks
+    -- XGMII clocksi
     clk_156                 : IN STD_LOGIC;    -- 156.25 MHz
     rst_156                 : IN STD_LOGIC;
 
@@ -390,6 +397,15 @@ BEGIN
     
     u_ip_arria10_e3sge3_phy_10gbase_r_24 : ip_arria10_e3sge3_phy_10gbase_r_24
     PORT MAP (
+      reconfig_write(0)       => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wr,                          -- in  std_logic_vector(0 downto 0)
+      reconfig_read(0)        => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.rd,                          -- in  std_logic_vector(0 downto 0)    
+      reconfig_address        => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.address(14 DOWNTO 0),        -- in  std_logic_vector(14 downto 0)   
+      reconfig_writedata      => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi.wrdata(c_word_w-1 DOWNTO 0), -- in  std_logic_vector(31 downto 0)   
+      reconfig_readdata       => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.rddata(c_word_w-1 DOWNTO 0), -- out std_logic_vector(31 downto 0);  
+      reconfig_waitrequest(0) => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso.waitrequest,                 -- out std_logic_vector(0 downto 0);   
+      reconfig_clk(0)         => mm_clk,                                                                  -- in  std_logic_vector(0 downto 0)    
+      reconfig_reset(0)       => mm_rst,                                                                -- in  std_logic_vector(0 downto 0)     
+
       tx_analogreset          => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0),          -- in  std_logic_vector(11 downto 0)   := (others => '0'); --          tx_analogreset.tx_analogreset
       tx_digitalreset         => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0),         -- in  std_logic_vector(11 downto 0)   := (others => '0'); --         tx_digitalreset.tx_digitalreset
       rx_analogreset          => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0),          -- in  std_logic_vector(11 downto 0)   := (others => '0'); --          rx_analogreset.rx_analogreset

libraries/technology/eth_10g/tech_eth_10g.vhd

@@ -107,6 +107,9 @@ ENTITY tech_eth_10g IS
     
     reg_eth10g_mosi  : IN  t_mem_mosi := c_mem_mosi_rst;  -- ETH10G (link status register)
     reg_eth10g_miso  : OUT t_mem_miso; 
+   
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
     
     -- ST
     tx_snk_in_arr    : IN  t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ 156 MHz
@@ -245,6 +248,9 @@ BEGIN
       
       reg_eth10g_mosi  => reg_eth10g_mosi,
       reg_eth10g_miso  => reg_eth10g_miso,
+
+      reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+      reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
       
       -- ST
       tx_snk_in_arr    => tx_snk_in_arr,       -- 64 bit data @ tr_ref_clk_156

libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd

@@ -117,7 +117,10 @@ ENTITY tech_eth_10g_arria10_e3sge3 IS
     mac_miso         : OUT t_mem_miso; 
     
     reg_eth10g_mosi  : IN  t_mem_mosi;         -- ETH10G (link status register)
-    reg_eth10g_miso  : OUT t_mem_miso; 
+    reg_eth10g_miso  : OUT t_mem_miso;
+
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi   : IN  t_mem_mosi := c_mem_mosi_rst; 
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso   : OUT t_mem_miso;
     
     -- ST
     tx_snk_in_arr    : IN  t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ clk_156
@@ -233,6 +236,11 @@ BEGIN
     g_nof_channels   => g_nof_channels
   )
   PORT MAP (
+   mm_clk              => mm_clk,
+   mm_rst              => mm_rst, 
+   reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+   reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
+
     -- Transceiver PLL reference clock
     tr_ref_clk_644     => tr_ref_clk_644,