added the "pll_clk200" ip block

libraries/technology/ip_arria10/pll_clk200/ip_arria10_pll_clk200.sopcinfo

@@ -5,11 +5,11 @@
  version="1.0"
  fabric="QSYS">
  <!-- Format version 14.0 374 (Future versions may contain additional information.) -->
- <!-- 2014.12.05.12:12:05 -->
+ <!-- 2014.12.05.12:19:49 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1417777925</value>
+  <value>1417778389</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>

libraries/technology/pll/hdllib.cfg

 hdl_lib_name = tech_pll
 hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks common
+hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks ip_arria10_pll_clk200 common
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR

libraries/technology/pll/tech_pll_clk200.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_pll_lib;
+LIBRARY ip_arria10_pll_clk200_altera_iopll_140;
 
 ENTITY tech_pll_clk200 IS
   GENERIC (
@@ -55,4 +56,16 @@ BEGIN
     PORT MAP (areset, inclk0, c0, c1, c2, locked);
   END GENERATE;
   
+  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+    u0 : ip_arria10_pll_clk200
+    PORT MAP (
+      rst      => areset, 
+      refclk   => inclk0, 
+      outclk_0 => c0, 
+      outclk_1 => c1, 
+      outclk_2 => c2, 
+      locked   => locked
+    );
+  END GENERATE;
+
 END ARCHITECTURE;

libraries/technology/pll/tech_pll_component_pkg.vhd

@@ -112,4 +112,17 @@ PACKAGE tech_pll_component_pkg IS
   );
   END COMPONENT;
 
+  COMPONENT ip_arria10_pll_clk200 IS
+  PORT
+  (
+    rst       : IN STD_LOGIC  := '0';
+    refclk    : IN STD_LOGIC  := '0';
+    outclk_0  : OUT STD_LOGIC ;
+    outclk_1  : OUT STD_LOGIC ;
+    outclk_2  : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
+  END COMPONENT;
+  
 END tech_pll_component_pkg;
+

libraries/technology/technology_select_pkg.vhd

@@ -30,7 +30,7 @@ USE work.technology_pkg.ALL;
 
 PACKAGE technology_select_pkg IS
 
-  CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
-  --CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
+  --CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+  CONSTANT c_tech_select_default : INTEGER := c_tech_arria10;
   
 END technology_select_pkg;