Remove g_technology, because it is c_tech_select_default.

libraries/base/reorder/src/vhdl/reorder_col.vhd

@@ -50,17 +50,15 @@
 --   is assumed that the reorder_col source is always fast enough. The reorder_col sink could
 --   support the input_siso signal, e.g. based on store_done and retrieve_done.
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_col is
   generic (
-    g_technology            : natural := c_tech_select_default;
     -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2 which
     -- is fine if no flow control is needed.
     g_use_output_rl_adapter : boolean := false;
@@ -168,7 +166,6 @@ begin
 
   u_store_buf : entity common_lib.common_paged_ram_r_w
   generic map (
-    g_technology      => g_technology,
     g_str             => "use_adr",
     g_data_w          => c_store_buf.dat_w,
     g_nof_pages       => c_data_nof_pages,
@@ -193,7 +190,6 @@ begin
 
   u_select_buf : entity common_lib.common_ram_crw_crw
   generic map (
-    g_technology => g_technology,
     g_ram        => c_select_buf,
     g_init_file  => g_select_file_name
   )

libraries/base/reorder/src/vhdl/reorder_col_select.vhd

@@ -46,17 +46,15 @@
 -- . Verified in tb_reorder_col_wide_row_select.vhd via reorder_col_wide_select
 --   that has g_nof_inputs instances of reorder_col_select.
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_col_select is
   generic (
-    g_technology  : natural := c_tech_select_default;
     g_dsp_data_w  : natural := 18;  -- complex data width, = c_data_w / 2
     g_nof_ch_in   : natural := 1024;
     g_nof_ch_sel  : natural := 12;
@@ -132,7 +130,6 @@ begin
 
   u_store_buf : entity common_lib.common_paged_ram_r_w
   generic map (
-    g_technology      => g_technology,
     g_str             => "use_adr",
     g_data_w          => c_store_buf.dat_w,
     g_nof_pages       => c_data_nof_pages,

libraries/base/reorder/src/vhdl/reorder_col_wide.vhd

@@ -30,17 +30,15 @@
 -- Remarks:
 --
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_col_wide is
   generic (
-    g_technology         : natural := c_tech_select_default;
     g_wb_factor          : natural := 4;
     g_dsp_data_w         : natural := 18;  -- complex data width, = c_data_w / 2
     g_nof_ch_in          : natural := 256;
@@ -101,7 +99,6 @@ begin
   gen_reorder_col_arr : for I in 0 to g_wb_factor - 1 generate
     u_reorder_col : entity work.reorder_col
     generic map (
-      g_technology         => g_technology,
       g_dsp_data_w         => g_dsp_data_w,
       g_nof_ch_in          => c_nof_ch_in,
       g_nof_ch_sel         => c_nof_ch_sel,

libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd

@@ -28,17 +28,15 @@
 -- Remarks:
 --
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_col_wide_select is
   generic (
-    g_technology         : natural := c_tech_select_default;
     g_nof_inputs         : natural := 6;
     g_dsp_data_w         : natural := 18;  -- complex data width, = c_data_w / 2
     g_nof_ch_in          : natural := 1024;
@@ -77,7 +75,6 @@ begin
   gen_nof_input : for I in 0 to g_nof_inputs - 1 generate
     u_reorder_col_select : entity work.reorder_col_select
     generic map (
-      g_technology         => g_technology,
       g_dsp_data_w         => g_dsp_data_w,
       g_nof_ch_in          => g_nof_ch_in,
       g_nof_ch_sel         => g_nof_ch_sel,

libraries/base/reorder/src/vhdl/reorder_matrix.vhd

@@ -46,17 +46,15 @@
 -- Remarks:
 --
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_matrix is
   generic (
-    g_technology            : natural := c_tech_select_default;
     g_nof_inputs            : natural := 24;
     g_nof_internals         : natural := 64;
     g_nof_outputs           : natural := 64;
@@ -118,7 +116,6 @@ begin
   -----------------------------------------------------------------------------
   u_input_reorder : entity work.reorder_row
   generic map(
-    g_technology        => g_technology,
     g_nof_inputs        => g_nof_inputs,
     g_nof_outputs       => g_nof_internals,
     g_dsp_data_w        => g_dsp_data_w,
@@ -148,7 +145,6 @@ begin
   -----------------------------------------------------------------------------
   u_ss_wide : entity work.reorder_col_wide
   generic map (
-    g_technology         => g_technology,
     g_wb_factor          => g_nof_internals,
     g_dsp_data_w         => g_dsp_data_w,
     g_nof_ch_in          => g_frame_size_in,
@@ -176,7 +172,6 @@ begin
   -----------------------------------------------------------------------------
   u_output_reorder : entity work.reorder_row
   generic map(
-    g_technology        => g_technology,
     g_nof_inputs        => g_nof_internals,
     g_nof_outputs       => g_nof_outputs,
     g_dsp_data_w        => g_dsp_data_w,

libraries/base/reorder/src/vhdl/reorder_row.vhd

@@ -31,17 +31,15 @@
 -- Remarks:
 --
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_row is
   generic (
-    g_technology    : natural := c_tech_select_default;
     g_dsp_data_w    : natural := 16;
     g_frame_size    : natural := 256;
     g_nof_inputs    : natural := 8;
@@ -109,11 +107,11 @@ architecture str of reorder_row is
 
   signal r, rin             : reg_type;
 
-  signal reorder_in_dat     : std_logic_vector(g_nof_inputs * c_data_w - 1    downto 0);
-  signal reorder_out_dat    : std_logic_vector(g_nof_outputs * c_data_w - 1   downto 0);
-  signal reorder_select     : std_logic_vector(c_mem_dat_w_dp - 1           downto 0);
+  signal reorder_in_dat     : std_logic_vector(g_nof_inputs * c_data_w - 1 downto 0);
+  signal reorder_out_dat    : std_logic_vector(g_nof_outputs * c_data_w - 1 downto 0);
+  signal reorder_select     : std_logic_vector(c_mem_dat_w_dp - 1 downto 0);
   --SIGNAL reorder_select     : STD_LOGIC_VECTOR(g_nof_outputs*c_select_w-1 DOWNTO 0);
-  signal reorder_chan_cnt   : std_logic_vector(c_select_buf_dp.adr_w - 1    downto 0);
+  signal reorder_chan_cnt   : std_logic_vector(c_select_buf_dp.adr_w - 1 downto 0);
 
 begin
   ---------------------------------------------------------------
@@ -165,7 +163,6 @@ begin
   ---------------------------------------------------------------
   u_select_buf : entity common_lib.common_ram_crw_crw_ratio
   generic map(
-    g_technology => g_technology,
     g_ram_a     => c_select_buf_mm,
     g_ram_b     => c_select_buf_dp,
     g_init_file => g_ram_init_file

libraries/base/reorder/src/vhdl/reorder_row_select.vhd

@@ -31,17 +31,15 @@
 -- Remarks:
 -- in_select always has to be defined on the same clock cycle as the in_sosi data.
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_row_select is
   generic (
-    g_technology    : natural := c_tech_select_default;
     g_dsp_data_w    : natural := 16;  -- complex data width, = c_data_w / 2
     g_nof_inputs    : natural := 8;
     g_nof_outputs   : natural := 16;

libraries/base/reorder/src/vhdl/reorder_transpose.vhd

@@ -75,18 +75,16 @@
 --   . g_use_complex =  TRUE : c_data_w = g_nof_streams*g_in_dat_w*c_nof_complex
 -- Remarks:
 
-library IEEE, common_lib, technology_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
 use common_lib.common_mem_pkg.all;
 use dp_lib.dp_stream_pkg.all;
 use work.reorder_pkg.all;
-use technology_lib.technology_select_pkg.all;
 
 entity reorder_transpose is
   generic(
-    g_technology     : natural := c_tech_select_default;
     g_pipeline_input : natural := 0;  -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
     g_pipeline_output: natural := 0;  -- choose 0 to have orignal version -r < 19416, choose 1 does not seem to help timing closure (erko)
     g_nof_streams    : natural := 4;
@@ -311,7 +309,6 @@ begin
 
     u_single_ss : entity work.reorder_col
     generic map (
-      g_technology         => g_technology,
       g_dsp_data_w         => c_data_w_pre,
       g_nof_ch_in          => c_nof_ch_in,
       g_nof_ch_sel         => c_nof_ch_sel,
@@ -375,7 +372,6 @@ begin
   ---------------------------------------------------------------
   u_sync_bsn_fifo : entity common_lib.common_fifo_sc
   generic map (
-    g_technology => g_technology,
     g_use_lut   => true,  -- Make this FIFO in logic, since it's only 2 words deep.
     g_reset     => false,
     g_init      => false,

libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd

@@ -31,7 +31,7 @@
 --   > Stop the simulation manually in Modelsim by pressing the stop-button.
 --   > Evalute u_dr_mem_ctrl/u_io_driver/ctlr_mosi in the WAVE window for wr and rd activity.
 
-library IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
+library IEEE, common_lib, mm_lib, diag_lib, dp_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
@@ -43,11 +43,8 @@ use mm_lib.mm_file_unb_pkg.all;
 use mm_lib.mm_file_pkg.all;
 use dp_lib.dp_stream_pkg.all;
 use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
-use tech_ddr_lib.tech_ddr_pkg.all;
 use work.reorder_pkg.all;
 
-
 entity tb_mms_reorder_rewire is
   generic (
     g_nof_streams      : positive := 8;

libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd

@@ -31,7 +31,7 @@
 --   > Stop the simulation manually in Modelsim by pressing the stop-button.
 --   > Evalute u_dr_mem_ctrl/u_io_driver/ctlr_mosi in the WAVE window for wr and rd activity.
 
-library IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
+library IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, tech_ddr_lib;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 use common_lib.common_pkg.all;
@@ -43,7 +43,6 @@ use mm_lib.mm_file_unb_pkg.all;
 use mm_lib.mm_file_pkg.all;
 use dp_lib.dp_stream_pkg.all;
 use diag_lib.diag_pkg.all;
-use technology_lib.technology_select_pkg.all;
 use tech_ddr_lib.tech_ddr_pkg.all;
 use work.reorder_pkg.all;
 
@@ -65,7 +64,6 @@ use work.reorder_pkg.all;
 --
 --
 
-
 entity tb_reorder_transpose is
   generic (
     g_wr_chunksize     : positive := 176;  -- 256;
@@ -342,7 +340,6 @@ begin
 
   u_ddr_mem_ctrl : entity io_ddr_lib.io_ddr
   generic map(
-    g_technology             => c_tech_select_default,  -- : NATURAL := c_tech_select_default;
     g_tech_ddr               => c_tech_ddr,  -- : t_c_tech_ddr;
     g_cross_domain_dvr_ctlr  => false,  -- TRUE,   --  : BOOLEAN := TRUE;
     g_wr_data_w              => c_data_w,  -- : NATURAL := 32;