Added tb_dp_xonoff.vhd.

libraries/base/dp/hdllib.cfg

@@ -166,6 +166,7 @@ test_bench_files =
     $UNB/Firmware/modules/dp/tb/vhdl/tb_dp_throttle_sop.vhd
     $UNB/Firmware/modules/dp/tb/vhdl/tb_mms_dp_fields.vhd
     tb/vhdl/tb_dp_sync_checker.vhd
+    tb/vhdl/tb_dp_xonoff.vhd
     
     $UNB/Firmware/modules/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
     $UNB/Firmware/modules/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd

libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Test bench for dp_xonoff
+-- Description:
+-- . Block diagram:
+--
+--     p_stimuli_st                               proc_dp_verify_*()
+--   
+--       stimuli_src_in                             verify_snk_out
+--       stimuli_src_out                            verify_snk_in 
+--               |   ____________________________    |
+--               |  | DUT                        |   |
+--               |  |                            |   |
+--            <-----| dut_snk_out     dut_src_in |<-----
+--            ----->| dut_snk_in      dut_src_out|-----> 
+--                  |____________________________|
+--
+--
+-- Usage:
+-- > as 10
+-- > run -all
+--
+-- Remarks:
+-- . Derived from tb_dp_example_no_dut.vhd
+-- 
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_lfsr_sequences_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE work.dp_stream_pkg.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY tb_dp_xonoff IS
+  GENERIC (
+    -- general
+    g_flow_control_stimuli   : t_dp_flow_control_enum := e_pulse;   -- always active, random or pulse flow control
+    g_flow_control_verify    : t_dp_flow_control_enum := e_active;  -- always active, random or pulse flow control
+    -- specific
+    g_in_dat_w               : NATURAL := 32;
+    g_in_nof_words           : NATURAL := 1;
+    g_nof_repeat             : NATURAL := 5;
+    g_pkt_len                : NATURAL := 16;  -- must be a multiple of g_in_nof_words
+    g_pkt_gap                : NATURAL := 4
+  );
+END tb_dp_xonoff;
+
+
+ARCHITECTURE tb OF tb_dp_xonoff IS
+
+  CONSTANT c_rl                       : NATURAL := 1;
+  
+  CONSTANT c_pulse_active             : NATURAL := g_in_nof_words;
+  CONSTANT c_pulse_period             : NATURAL := g_in_nof_words;
+  
+  CONSTANT c_sync_period              : NATURAL := 10;
+  CONSTANT c_sync_offset              : NATURAL := 7;
+  
+  CONSTANT c_data_max                 : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
+  CONSTANT c_data_init                : INTEGER := -1;
+  CONSTANT c_bsn_init                 : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000";  -- X"0877665544332211"
+  CONSTANT c_err_init                 : NATURAL := 247;
+  CONSTANT c_channel_init             : INTEGER := 5;  -- fixed
+  
+  SIGNAL tb_end                     : STD_LOGIC := '0';
+  SIGNAL clk                        : STD_LOGIC := '1';
+  SIGNAL rst                        : STD_LOGIC := '1';
+  SIGNAL sl1                        : STD_LOGIC := '1';
+  
+  SIGNAL random_0                   : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0');  -- use different lengths to have different random sequences
+  SIGNAL random_1                   : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0');  -- use different lengths to have different random sequences
+  SIGNAL pulse_0                    : STD_LOGIC;
+  SIGNAL pulse_1                    : STD_LOGIC;
+  SIGNAL pulse_en                   : STD_LOGIC := '1';
+  
+  SIGNAL stimuli_en                 : STD_LOGIC := '1';
+  SIGNAL stimuli_src_in             : t_dp_siso;
+  SIGNAL stimuli_src_out            : t_dp_sosi;
+  SIGNAL stimuli_data               : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+  
+  SIGNAL dut_snk_out                : t_dp_siso;
+  SIGNAL dut_snk_in                 : t_dp_sosi;
+  
+  SIGNAL dut_src_in                 : t_dp_siso;
+  SIGNAL dut_src_out                : t_dp_sosi;
+  
+  SIGNAL prev_verify_snk_out        : t_dp_siso;
+  SIGNAL verify_snk_out             : t_dp_siso := c_dp_siso_rdy;
+  SIGNAL verify_snk_in              : t_dp_sosi;
+  SIGNAL verify_snk_in_data         : STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);  -- used to hold valid data for verify at verify_done
+  SIGNAL verify_data                : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
+  SIGNAL prev_verify_snk_in         : t_dp_sosi;
+  
+  SIGNAL verify_hold_sop            : STD_LOGIC := '0';
+  SIGNAL verify_en_valid            : STD_LOGIC := '0';
+  SIGNAL verify_en_sop              : STD_LOGIC := '0';
+  SIGNAL verify_en_eop              : STD_LOGIC := '0';
+  SIGNAL verify_done                : STD_LOGIC := '0';  
+  
+  SIGNAL expected_verify_snk_in     : t_dp_sosi;
+  
+BEGIN
+
+  clk <= (NOT clk) OR tb_end AFTER clk_period/2;
+  rst <= '1', '0' AFTER clk_period*7;
+  
+  random_0 <= func_common_random(random_0) WHEN rising_edge(clk);
+  random_1 <= func_common_random(random_1) WHEN rising_edge(clk);
+  
+  proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period,   '1', rst, clk, pulse_en, pulse_0);
+  proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period+1, '1', rst, clk, pulse_en, pulse_1);
+
+  ------------------------------------------------------------------------------
+  -- STREAM CONTROL
+  ------------------------------------------------------------------------------
+  
+  stimuli_en           <= '1'                     WHEN g_flow_control_stimuli=e_active ELSE
+                          random_0(random_0'HIGH) WHEN g_flow_control_stimuli=e_random ELSE
+                          pulse_0                 WHEN g_flow_control_stimuli=e_pulse;
+                       
+  verify_snk_out.ready <= '1'                     WHEN g_flow_control_verify=e_active  ELSE
+                          random_1(random_1'HIGH) WHEN g_flow_control_verify=e_random  ELSE
+                          pulse_1                 WHEN g_flow_control_verify=e_pulse;
+  
+  
+  ------------------------------------------------------------------------------
+  -- DATA GENERATION
+  ------------------------------------------------------------------------------
+  
+  -- Generate data path input data
+  p_stimuli_st : PROCESS
+    VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
+  BEGIN
+    -- Adjust initial sosi field values by -1 to compensate for auto increment
+    v_sosi.bsn     := INCR_UVEC(c_bsn_init,                    -1);
+    v_sosi.channel := INCR_UVEC(TO_DP_CHANNEL(c_channel_init), -1);
+    v_sosi.data    := INCR_UVEC(TO_DP_DATA(c_data_init),       -1);
+    v_sosi.err     := INCR_UVEC(TO_DP_ERROR(c_err_init),       -1);
+    
+    stimuli_src_out <= c_dp_sosi_rst;
+    proc_common_wait_until_low(clk, rst);
+    proc_common_wait_some_cycles(clk, 5);
+
+    -- Generate c_nof_repeat packets
+    FOR I IN 0 TO g_nof_repeat-1 LOOP
+      -- Auto increment v_sosi field values for this packet
+      v_sosi.bsn     := INCR_UVEC(v_sosi.bsn, 1);
+      v_sosi.sync    := sel_a_b((UNSIGNED(v_sosi.bsn) MOD c_sync_period) = c_sync_offset, '1', '0');  -- insert sync starting at BSN=c_sync_offset and with period c_sync_period
+      v_sosi.channel := INCR_UVEC(v_sosi.channel, 1);
+      v_sosi.data    := INCR_UVEC(v_sosi.data, g_pkt_len);
+      v_sosi.data    := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0));  -- wrap when >= 2**g_in_dat_w
+      v_sosi.err     := INCR_UVEC(v_sosi.err, 1);
+      
+      -- Send packet
+      proc_dp_gen_block_data(g_in_dat_w, TO_UINT(v_sosi.data), g_pkt_len, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, clk, stimuli_en, stimuli_src_in, stimuli_src_out);
+      
+      -- Insert optional gap between the packets
+      proc_common_wait_some_cycles(clk, g_pkt_gap);
+    END LOOP;
+    
+    -- Determine expected sosi field values after end of stimuli
+    -- . e_qual
+    v_sosi.bsn     := STD_LOGIC_VECTOR( UNSIGNED(c_bsn_init) + g_nof_repeat-1);
+    v_sosi.channel := TO_DP_CHANNEL(c_channel_init           + g_nof_repeat-1);
+    v_sosi.err     := TO_DP_ERROR(c_err_init                 + g_nof_repeat-1);
+    -- . account for g_pkt_len
+    v_sosi.data    := INCR_UVEC(v_sosi.data, g_pkt_len-1);
+    v_sosi.data    := RESIZE_DP_DATA(v_sosi.data(g_in_dat_w-1 DOWNTO 0));  -- wrap when >= 2**g_in_dat_w
+    expected_verify_snk_in <= v_sosi;
+    
+    -- Signal end of stimuli
+    proc_common_wait_some_cycles(clk, 100);  -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+    proc_common_gen_pulse(clk, verify_done);
+    proc_common_wait_some_cycles(clk, 50);
+    tb_end <= '1';
+    WAIT;
+  END PROCESS;
+  
+  
+  ------------------------------------------------------------------------------
+  -- DATA VERIFICATION
+  ------------------------------------------------------------------------------
+  
+  -- Start verify after first valid, sop or eop
+  verify_en_valid <= '1' WHEN verify_snk_in.valid='1' AND rising_edge(clk);
+  verify_en_sop   <= '1' WHEN verify_snk_in.sop='1'   AND rising_edge(clk);
+  verify_en_eop   <= '1' WHEN verify_snk_in.eop='1'   AND rising_edge(clk);
+  
+  -- Verify that the stimuli have been applied at all
+  proc_dp_verify_value("verify_snk_in.valid",            clk, verify_done, sl1, verify_en_valid);
+  proc_dp_verify_value("verify_snk_in.sop",              clk, verify_done, sl1, verify_en_sop);
+  proc_dp_verify_value("verify_snk_in.eop",              clk, verify_done, sl1, verify_en_eop);
+  proc_dp_verify_value("verify_snk_in.data",    e_equal, clk, verify_done, expected_verify_snk_in.data,    verify_snk_in_data);
+  --proc_dp_verify_value("verify_snk_in.bsn",     e_equal, clk, verify_done, expected_verify_snk_in.bsn,     verify_snk_in.bsn);
+  --proc_dp_verify_value("verify_snk_in.channel", e_equal, clk, verify_done, expected_verify_snk_in.channel, verify_snk_in.channel);
+  --proc_dp_verify_value("verify_snk_in.err",     e_equal, clk, verify_done, expected_verify_snk_in.err,     verify_snk_in.err);
+  
+  -- Verify that the output is incrementing data, like the input stimuli
+  proc_dp_verify_data("verify_snk_in.data",    c_rl, c_data_max,   c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data,    prev_verify_snk_in.data);
+  --proc_dp_verify_data("verify_snk_in.bsn",     c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop,   verify_snk_out.ready, verify_snk_in.sop,   verify_snk_in.bsn,     prev_verify_snk_in.bsn);
+  --proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_sop,   verify_snk_out.ready, verify_snk_in.sop,   verify_snk_in.channel, prev_verify_snk_in.channel);
+  --proc_dp_verify_data("verify_snk_in.err",     c_rl, c_unsigned_0, c_unsigned_1, clk, verify_en_eop,   verify_snk_out.ready, verify_snk_in.eop,   verify_snk_in.err,     prev_verify_snk_in.err);
+  
+  -- Verify that the output sync occurs when expected
+  --proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en_sop, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn);
+  
+  -- Verify output packet ctrl
+  proc_dp_verify_sop_and_eop(clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, verify_hold_sop);
+  
+  -- Verify output ready latency
+  proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
+  
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  
+  -- Connect stimuli input stream to DUT sink
+  stimuli_src_in <= dut_snk_out;
+  dut_snk_in     <= stimuli_src_out;
+  
+  -- DUT function
+  u_dut : ENTITY work.dp_xonoff
+  PORT MAP (
+    rst           => rst,
+    clk           => clk,
+    -- Frame in
+    in_siso       => dut_snk_out,
+    in_sosi       => dut_snk_in,
+    -- Frame out
+    out_siso      => dut_src_in,  -- flush control via out_siso.xon
+    out_sosi      => dut_src_out
+  );  
+
+  
+    
+  -- Connect DUT source output stream to verification
+  dut_src_in     <= verify_snk_out;
+  verify_snk_in  <= dut_src_out;
+
+  
+  ------------------------------------------------------------------------------
+  -- Auxiliary
+  ------------------------------------------------------------------------------
+  
+  -- Map to slv to ease monitoring in wave window
+  stimuli_data <= stimuli_src_out.data(g_in_dat_w-1 DOWNTO 0);
+  verify_data  <= verify_snk_in.data(g_in_dat_w-1 DOWNTO 0);
+  
+  verify_snk_in_data <= verify_snk_in.data WHEN verify_snk_in.valid='1';
+END tb;