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RTSD
HDL
Commits
264b1e6c
Commit
264b1e6c
authored
9 years ago
by
Eric Kooistra
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Made tb self stopping.
parent
cd9246e3
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libraries/base/util/tb/vhdl/tb_util_heater.vhd
+6
-3
6 additions, 3 deletions
libraries/base/util/tb/vhdl/tb_util_heater.vhd
with
6 additions
and
3 deletions
libraries/base/util/tb/vhdl/tb_util_heater.vhd
+
6
−
3
View file @
264b1e6c
...
@@ -51,6 +51,7 @@ ARCHITECTURE tb OF tb_util_heater IS
...
@@ -51,6 +51,7 @@ ARCHITECTURE tb OF tb_util_heater IS
CONSTANT
c_reg_nof_words
:
NATURAL
:
=
2
;
-- derived from c_nof_mac4 / c_word_w
CONSTANT
c_reg_nof_words
:
NATURAL
:
=
2
;
-- derived from c_nof_mac4 / c_word_w
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
mm_rst
:
STD_LOGIC
;
SIGNAL
mm_rst
:
STD_LOGIC
;
SIGNAL
mm_clk
:
STD_LOGIC
:
=
'0'
;
SIGNAL
mm_clk
:
STD_LOGIC
:
=
'0'
;
SIGNAL
st_rst
:
STD_LOGIC
;
SIGNAL
st_rst
:
STD_LOGIC
;
...
@@ -62,10 +63,10 @@ ARCHITECTURE tb OF tb_util_heater IS
...
@@ -62,10 +63,10 @@ ARCHITECTURE tb OF tb_util_heater IS
BEGIN
BEGIN
-- as 10
-- as 10
-- run
20 us
-- run
-all
mm_clk
<=
NOT
mm_clk
AFTER
mm_clk_period
/
2
;
mm_clk
<=
NOT
mm_clk
OR
tb_end
AFTER
mm_clk_period
/
2
;
st_clk
<=
NOT
st_clk
AFTER
st_clk_period
/
2
;
st_clk
<=
NOT
st_clk
OR
tb_end
AFTER
st_clk_period
/
2
;
mm_rst
<=
'1'
,
'0'
AFTER
mm_clk_period
*
5
;
mm_rst
<=
'1'
,
'0'
AFTER
mm_clk_period
*
5
;
st_rst
<=
'1'
,
'0'
AFTER
st_clk_period
*
5
;
st_rst
<=
'1'
,
'0'
AFTER
st_clk_period
*
5
;
...
@@ -99,6 +100,8 @@ BEGIN
...
@@ -99,6 +100,8 @@ BEGIN
FOR
I
IN
0
TO
c_time_heater_off
-1
LOOP
FOR
I
IN
0
TO
c_time_heater_off
-1
LOOP
WAIT
UNTIL
rising_edge
(
mm_clk
);
WAIT
UNTIL
rising_edge
(
mm_clk
);
END
LOOP
;
END
LOOP
;
tb_end
<=
'1'
;
WAIT
;
END
PROCESS
;
END
PROCESS
;
dut
:
ENTITY
work
.
util_heater
dut
:
ENTITY
work
.
util_heater
...
...
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