L2SDP-206, back to original.

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -54,7 +54,7 @@ ENTITY node_adc_input_and_timing IS
     dp_rst                         : IN STD_LOGIC;
 
     -- mm control buses
-    -- JESD control
+    -- JESD 
     jesd204b_mosi                  : IN  t_mem_mosi := c_mem_mosi_rst;
     jesd204b_miso                  : OUT t_mem_miso := c_mem_miso_rst; 
  
@@ -98,10 +98,6 @@ ENTITY node_adc_input_and_timing IS
     reg_aduh_monitor_mosi          : IN  t_mem_mosi;
     reg_aduh_monitor_miso          : OUT t_mem_miso;
 
-    -- JESD reset control
-    jesd_ctrl_mosi                 : IN  t_mem_mosi;
-    jesd_ctrl_miso                 : OUT t_mem_miso;
-
     -- JESD io signals
     JESD204B_SERIAL_DATA           : IN    STD_LOGIC_VECTOR((c_sdp_jesd204b_bus_w*c_sdp_jesd204b_nof_bus)-1 downto 0); 
     JESD204B_REFCLK                : IN    STD_LOGIC; 
@@ -121,12 +117,6 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
   CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
   CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
 
-  CONSTANT c_mm_jesd_ctrl_reg       : t_c_mem := (latency  => 1,
-                                                  adr_w    => 1,
-                                                  dat_w    => c_word_w,
-                                                  nof_dat  => 1,
-                                                  init_sl  => '0');
-
   -- Waveform Generator
   CONSTANT c_wg_buf_directory       : STRING := "data/";
   CONSTANT c_wg_buf_dat_w           : NATURAL := 18; --default value of WG that fits 14 bits of ADC data
@@ -162,25 +152,9 @@ ARCHITECTURE str OF node_adc_input_and_timing IS
   SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
 
-  SIGNAL mm_rst_internal            : STD_LOGIC; 
-  SIGNAL mm_jesd_ctrl_reg           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-  SIGNAL jesd204b_disable_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
 
 BEGIN
 
-  -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-  -- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-  -- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
-  -- The MM jesd204b_reset should not be applied in an SDP application, because this will cause
-  -- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
-  -- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-  -- complete blocks, so from sop to eop.
-
-  mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31);
-  gen_jesd_disable : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
-    jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
-  END GENERATE;
-
   -----------------------------------------------------------------------------
   -- JESD204B IP (ADC Handler)
   -----------------------------------------------------------------------------
@@ -202,8 +176,6 @@ BEGIN
     rx_rst               => rx_rst,          
     rx_sysref            => rx_sysref,          
   
-    jesd204b_disable_arr  => jesd204b_disable_arr,
-
     -- MM
     mm_clk               => mm_clk,           
     mm_rst               => mm_rst,           
@@ -225,29 +197,6 @@ BEGIN
     diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
   END GENERATE;
 
-  -----------------------------------------------------------------------------
-  -- JESD Control register
-  -----------------------------------------------------------------------------
-  u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
-  GENERIC MAP (
-    g_reg       => c_mm_jesd_ctrl_reg,
-    g_init_reg  => (OTHERS => '0')
-  )
-  PORT MAP (
-    rst       => mm_rst,
-    clk       => mm_clk,
-    -- control side
-    wr_en     => jesd_ctrl_mosi.wr,
-    wr_adr    => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
-    wr_dat    => jesd_ctrl_mosi.wrdata(c_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
-    rd_en     => jesd_ctrl_mosi.rd,
-    rd_adr    => jesd_ctrl_mosi.address(c_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
-    rd_dat    => jesd_ctrl_miso.rddata(c_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
-    rd_val    => OPEN,
-    -- data side
-    out_reg   => mm_jesd_ctrl_reg,
-    in_reg    => mm_jesd_ctrl_reg
-  );
 
   -----------------------------------------------------------------------------
   -- Diagnostic Data Buffer (Records 1024 raw ADC samples after the PPS)