From master

applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt

@@ -81,12 +81,6 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
 - Buffer lengte versus nof antennes
 - Self trigger
 
-<<<<<<< HEAD
-3) Design
-
-- buffer raw data, no need to buffer subbands
-- no self triggering yet for MVP
-=======
 
 3) TBB (Transient Buffer Board) LOFAR1
 - From 2.3 in [4]
@@ -102,18 +96,11 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
 
 - choose fixe 14b data, so not e.g. 8 Msbits for lighting and 8 Lsbits for
   cosmic ray. Always using full W_adc = 14b makes design and usage more clear.
->>>>>>> master
 
 - Station --> CEP --> Data Writer
   . SDP output UDP directly to CEP or to LCU so that LCU can pass it on via TCP, to
     recover from data loss
   . SDP output via 10GbE
-<<<<<<< HEAD
-  . SDP CP for speed dial output, to avoid data loss
-
-- treat all signal inputs independently (even though X and Y are always needed together)
-
-=======
   . SDP CP for speed dial (= throttle) output, to avoid data loss
 
 - treat all signal inputs independently (even though X and Y are always needed together)
@@ -128,14 +115,11 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
   . TBuf does not need sync ?
   . Start SSN or mem BSN at same time as SDP BSN by FPGA_processing_enable_RW.
 
->>>>>>> master
 - CP per signal input buffer
   . flexible start and end address (so flexible buffer time per signal input)
   . freeze, unfreeze
   . no need to whipe (zero) buffer contents after unfreeze ?
 
-<<<<<<< HEAD
-=======
 - State
   . rst --> stop <--> record
 
@@ -149,7 +133,6 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
        . 1 MM
        . 1 retrieve --> unpack 256b to 64b --> check CRC --> add output hdr --> dump
 
->>>>>>> master
 - support MP on buffer state
   . signal input index
   . frozen, buffering, reading
@@ -157,13 +140,8 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
 
 - Provide direct MM access interface to DDR4
   . New access multiplexer component to interface with io_ddr with:
-<<<<<<< HEAD
-    . write 12 signal input streams + 1 MM write stream
-    . read 1 stream for TB readout + 1 MM read stream
-=======
     . write 12 signal input streams for TBuf recording + 1 MM write stream
     . read 1 stream for TBuf readout + 1 MM read stream
->>>>>>> master
   . Write multiplexer for 12 + 1 = 13 inputs will take ~100 M20K,
     because it needs to multiplex and FIFO streams of 256 bit each and
     256 bit requires 256 /40 = 7 M20K in parallel, so 13 * 7 = 91 M20K.
@@ -171,29 +149,17 @@ Design decision 16GByte DDR4 na L2SDP-854, 850
     16 kByte, so FIFO can fit (almost) two 8 kB payloads, which seems
     sufficient.
 
-<<<<<<< HEAD
-Use 1 DDR4 module / FPGA
-  . Because 16GB is enough for T_tbuf = 3.3 s
-  . 1 DDR4 @ 200MHz yields 200MHz * 256b/8b = 6.4 GB/s maximum write
-    access. Samples data from 12 ADCs is 12 * 200MHz * 16b/8b = 4.8 GB/s.
-    Hence the TB function then uses 4.8 / 6.4 = 0.75 of the capacity,
-=======
 - Use 1 DDR4 module / FPGA
   . Because 16GB is enough for T_tbuf = 3.3 s
   . 1 DDR4 @ 200MHz yields 200MHz * 256b/8b = 6.4 GB/s maximum write
     access. Samples data from 12 ADCs is 12 * 200MHz * 16b/8b = 4.8 GB/s.
     Hence the TBuf function then uses 4.8 / 6.4 = 0.75 of the capacity,
->>>>>>> master
     which is fine and leaves sufficient spare capacity for some buffer
     read out, because 10Gbps / 8b = maximum 1.2 GB/s.
   . If we would use 2 DDR4 modules/ FPGA, then treat them as one big
     buffer with extended address space by DDR4 II, so use them
     sequentially, rather than in parallel, and to still have full
-<<<<<<< HEAD
-    freedom of allocationg memory space to signal inputs.
-=======
     freedom of allocating memory space to signal inputs.
->>>>>>> master
 
 - support partial dump
   . lightning >~ 1 s, cosmic ray >~ 1 ms
@@ -204,11 +170,6 @@ Use 1 DDR4 module / FPGA
   . packtetize at 64b or 256b ?
   . 16b -> 64b packetize --> 64b --> 256b store
   . data in buffer must have CRC --> 64b CRC ?
-<<<<<<< HEAD
-
-- dp_offload_tx header is the same for all 12 signal inputs, only si differs,
-  so create one header for all and modify si field to save logic and RAM
-=======
   . ddr page packet format: SSN + packed data + CRC
     - 8 KByte page to have integer number of pages (= slots) in 16G memory, so
       that DDR4-I can wrap without a gap or extend to DDR-II without a gap.
@@ -225,7 +186,6 @@ Use 1 DDR4 module / FPGA
   . add additional eth/ip/udp header and application header
   . send packed 14b data
 
->>>>>>> master
 - 12 input multiplexer with 12 x 256b in and 256b out to write 256b words @ 200 MHz
 - use SSN as timestamp, SSN = BSN * N_fft, so can be derived from bsn_source BSN,
   or do we need a dp_ssn_source.vhd?
@@ -255,11 +215,6 @@ Use 1 DDR4 module / FPGA
 - Maximum number of packets per dump
   . max memory size 16GB
   . max payload size 8kB
-<<<<<<< HEAD
-  --> 16G / 8k = 2M packets --> log2(2e6) = 20.93b
-  . use packet serial number, instead of sop, eop bit fields, to show progress of
-    the packet dump to CEP
-=======
   --> 16G / 8k = 2M packets --> log2(2M) = 21b
   . use packet serial number, instead of sop, eop bit fields, to show progress of
     the packet dump to CEP
@@ -300,7 +255,6 @@ Use 1 DDR4 module / FPGA
 
 
 6) TBuf ICD STAT/SDP-CEP
->>>>>>> master
 
 - application header fields:
   . 8b marker
@@ -310,11 +264,7 @@ Use 1 DDR4 module / FPGA
     - 1b antenna_band_index
     - 1b nyquist_zone_index
     - 1b f_adc --> sample period is 5 ns or 6.25 ns
-<<<<<<< HEAD
-    - 1b payload_error --> based on DDR4 read CRC
-=======
     - 1b memory_error --> based on DDR4 read CRC
->>>>>>> master
     - 5b sample_width --> 14b
   . 8b signal_input_index
   . 16b nof_samples_per_packet
@@ -326,9 +276,6 @@ Use 1 DDR4 module / FPGA
     - 5b gn_index --> signal_input_index provides already all this information
 
 
-<<<<<<< HEAD
-
-=======
 7) Transient detection (TDet) Design
 
 - no self triggering yet for MVP
@@ -346,4 +293,3 @@ Use 1 DDR4 module / FPGA
   magnitude response doesn't have to be 0 at π, therefore they have increased
   bandwidths. So for odd length filters the useful bandwidth is limited to
   0 < w < π.
->>>>>>> master