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RTSD
HDL
Commits
238c8698
Commit
238c8698
authored
2 years ago
by
Eric Kooistra
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Improve test coverage.
parent
4c19ddf7
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1 merge request
!272
L2SDP-801 Verify bsn time offset in dp_bsn_source_v2.vhd
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libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+33
-12
33 additions, 12 deletions
libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+29
-15
29 additions, 15 deletions
libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
with
62 additions
and
27 deletions
libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+
33
−
12
View file @
238c8698
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
--
-- Copyright (C) 20
11
-- Copyright (C) 20
20
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--
...
@@ -25,9 +25,9 @@
...
@@ -25,9 +25,9 @@
-- [1].
-- [1].
-- Decsription:
-- Decsription:
-- * Start/Stop BSN source tests:
-- * Start/Stop BSN source tests:
-- 1) test
1x
asynchronously (dp_on_pps='0') without automatic check, check
-- 1) test
once
asynchronously (dp_on_pps='0') without automatic check, check
-- visualy in wave window.
-- visualy in wave window.
-- 2) test
3x
synchronously (dp_on_pps='1') with automatic check.
-- 2) test
c_nof_repeat
synchronously (dp_on_pps='1') with automatic check.
-- . Verify if bs_sosi.eop and bs_sosi.sop come in pairs
-- . Verify if bs_sosi.eop and bs_sosi.sop come in pairs
-- . Verify that bs_sosi.sync is at bs_sosi.sop
-- . Verify that bs_sosi.sync is at bs_sosi.sop
-- . Verify that bs_sosi has fixed latency with respect to ref_grid
-- . Verify that bs_sosi has fixed latency with respect to ref_grid
...
@@ -37,7 +37,7 @@
...
@@ -37,7 +37,7 @@
-- [2] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+source+with+offset
-- [2] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+BSN+source+with+offset
--
--
-- Usage:
-- Usage:
-- > as
10
-- > as
8, e.g. view bs_sosi, exp_grid and unexpected_bs_sync
-- > run -all
-- > run -all
-- . sop, eop are verified automatically
-- . sop, eop are verified automatically
-- . sync and bsn are verified automatically using the ref_grid
-- . sync and bsn are verified automatically using the ref_grid
...
@@ -52,15 +52,22 @@ USE dp_lib.tb_dp_pkg.ALL;
...
@@ -52,15 +52,22 @@ USE dp_lib.tb_dp_pkg.ALL;
ENTITY
tb_dp_bsn_source_v2
IS
ENTITY
tb_dp_bsn_source_v2
IS
GENERIC
(
GENERIC
(
g_nof_pps
:
NATURAL
:
=
10
;
g_pps_interval
:
NATURAL
:
=
16
;
--101;
g_pps_interval
:
NATURAL
:
=
10
;
--101;
g_block_size
:
NATURAL
:
=
5
--23
g_block_size
:
NATURAL
:
=
7
--23
);
);
END
tb_dp_bsn_source_v2
;
END
tb_dp_bsn_source_v2
;
ARCHITECTURE
tb
OF
tb_dp_bsn_source_v2
IS
ARCHITECTURE
tb
OF
tb_dp_bsn_source_v2
IS
CONSTANT
c_nof_repeat
:
NATURAL
:
=
3
;
CONSTANT
c_gcd
:
NATURAL
:
=
gcd
(
g_pps_interval
,
g_block_size
);
CONSTANT
c_min_nof_interval
:
NATURAL
:
=
g_block_size
/
c_gcd
;
-- choose c_nof_pps and c_nof_repeat > c_min_nof_interval, because the
-- fractional sync pattern will repeat every c_min_nof_interval number
-- of g_pps_intervals.
CONSTANT
c_factor
:
NATURAL
:
=
3
;
CONSTANT
c_nof_pps
:
NATURAL
:
=
c_min_nof_interval
*
c_factor
;
CONSTANT
c_nof_repeat
:
NATURAL
:
=
c_min_nof_interval
*
c_factor
;
CONSTANT
c_clk_period
:
TIME
:
=
10
ns
;
CONSTANT
c_clk_period
:
TIME
:
=
10
ns
;
CONSTANT
c_bsn_w
:
NATURAL
:
=
31
;
CONSTANT
c_bsn_w
:
NATURAL
:
=
31
;
...
@@ -119,6 +126,9 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
...
@@ -119,6 +126,9 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
SIGNAL
prev_bs_valid
:
STD_LOGIC
;
SIGNAL
prev_bs_valid
:
STD_LOGIC
;
SIGNAL
bs_starts_cnt
:
NATURAL
:
=
0
;
SIGNAL
bs_starts_cnt
:
NATURAL
:
=
0
;
SIGNAL
dbg_c_nof_pps
:
NATURAL
:
=
c_nof_pps
;
SIGNAL
dbg_c_nof_repeat
:
NATURAL
:
=
c_nof_repeat
;
SIGNAL
dbg_nof_blk
:
NATURAL
;
SIGNAL
dbg_nof_blk
:
NATURAL
;
SIGNAL
dbg_accumulate
:
NATURAL
;
SIGNAL
dbg_accumulate
:
NATURAL
;
SIGNAL
dbg_expected_bsn
:
NATURAL
;
SIGNAL
dbg_expected_bsn
:
NATURAL
;
...
@@ -181,7 +191,7 @@ BEGIN
...
@@ -181,7 +191,7 @@ BEGIN
tb_state
<=
s_dp_on
;
tb_state
<=
s_dp_on
;
dp_on_pps
<=
'0'
;
dp_on_pps
<=
'0'
;
dp_on
<=
'1'
;
dp_on
<=
'1'
;
proc_common_wait_some_cycles
(
clk
,
g
_nof_pps
*
g_pps_interval
);
proc_common_wait_some_cycles
(
clk
,
c
_nof_pps
*
g_pps_interval
);
tb_state
<=
s_disable
;
tb_state
<=
s_disable
;
dp_on
<=
'0'
;
dp_on
<=
'0'
;
dp_on_pps
<=
'0'
;
dp_on_pps
<=
'0'
;
...
@@ -212,7 +222,7 @@ BEGIN
...
@@ -212,7 +222,7 @@ BEGIN
tb_state
<=
s_dp_on_pps
;
tb_state
<=
s_dp_on_pps
;
dp_on_pps
<=
'1'
;
dp_on_pps
<=
'1'
;
dp_on
<=
'1'
;
dp_on
<=
'1'
;
proc_common_wait_some_cycles
(
clk
,
g
_nof_pps
*
g_pps_interval
);
proc_common_wait_some_cycles
(
clk
,
c
_nof_pps
*
g_pps_interval
);
tb_state
<=
s_disable
;
tb_state
<=
s_disable
;
dp_on
<=
'0'
;
dp_on
<=
'0'
;
dp_on_pps
<=
'0'
;
dp_on_pps
<=
'0'
;
...
@@ -238,7 +248,8 @@ BEGIN
...
@@ -238,7 +248,8 @@ BEGIN
--proc_dp_verify_sync(clk, verify_sync, bs_sosi.sync, exp_grid.sop, exp_grid.sync); -- Verify sync at sop and at expected_sync
--proc_dp_verify_sync(clk, verify_sync, bs_sosi.sync, exp_grid.sop, exp_grid.sync); -- Verify sync at sop and at expected_sync
-- Verify sync at sop and at expected_sync
-- Verify sync at sop and at expected_sync
proc_dp_verify_sync
(
g_pps_interval
,
proc_dp_verify_sync
(
0
,
-- start bsn of PPS grid and BSN grid is 0, see [1]
g_pps_interval
,
g_block_size
,
g_block_size
,
clk
,
clk
,
verify_en
,
verify_en
,
...
@@ -267,10 +278,20 @@ BEGIN
...
@@ -267,10 +278,20 @@ BEGIN
END
IF
;
END
IF
;
END
PROCESS
;
END
PROCESS
;
-- Verify that bs_sosi.valid = '1' did happen after dp_on
-- Verify that bs_sosi.valid = '1' did happen after dp_on
by verifying bs_start
prev_bs_valid
<=
bs_sosi
.
valid
WHEN
rising_edge
(
clk
);
prev_bs_valid
<=
bs_sosi
.
valid
WHEN
rising_edge
(
clk
);
bs_starts_cnt
<=
bs_starts_cnt
+
1
WHEN
rising_edge
(
clk
)
AND
bs_sosi
.
valid
=
'1'
AND
prev_bs_valid
=
'0'
;
bs_starts_cnt
<=
bs_starts_cnt
+
1
WHEN
rising_edge
(
clk
)
AND
bs_sosi
.
valid
=
'1'
AND
prev_bs_valid
=
'0'
;
p_verify_bs_restart
:
PROCESS
(
clk
)
BEGIN
IF
rising_edge
(
clk
)
THEN
IF
bs_restart
=
'1'
THEN
ASSERT
bs_sosi
.
sync
=
'1'
REPORT
"Unexpected bs_start while bs_sosi.sync /= 1"
SEVERITY
ERROR
;
ASSERT
prev_bs_valid
=
'0'
REPORT
"Unexpected bs_start while prev_bs_valid /= 0"
SEVERITY
ERROR
;
END
IF
;
END
IF
;
END
PROCESS
;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- DUT: dp_bsn_source_v2
-- DUT: dp_bsn_source_v2
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
...
...
This diff is collapsed.
Click to expand it.
libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+
29
−
15
View file @
238c8698
...
@@ -25,7 +25,7 @@ USE IEEE.std_logic_1164.ALL;
...
@@ -25,7 +25,7 @@ USE IEEE.std_logic_1164.ALL;
USE
work
.
tb_dp_pkg
.
ALL
;
USE
work
.
tb_dp_pkg
.
ALL
;
-- > as
2
-- > as
4
-- > run -all --> OK
-- > run -all --> OK
ENTITY
tb_tb_dp_bsn_source_v2
IS
ENTITY
tb_tb_dp_bsn_source_v2
IS
...
@@ -33,30 +33,44 @@ END tb_tb_dp_bsn_source_v2;
...
@@ -33,30 +33,44 @@ END tb_tb_dp_bsn_source_v2;
ARCHITECTURE
tb
OF
tb_tb_dp_bsn_source_v2
IS
ARCHITECTURE
tb
OF
tb_tb_dp_bsn_source_v2
IS
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
-- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
CONSTANT
c_nof_pps
:
NATURAL
:
=
50
;
-- choose > g_block_size, because the fractional sync pattern will repeat
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
-- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-- within g_block_size number of g_pps_interval's
BEGIN
BEGIN
-- from tb_dp_bsn_source_v2.vhd
-- from tb_dp_bsn_source_v2.vhd
--
--
-- g_nof_pps : NATURAL := 20;
-- g_pps_interval : NATURAL := 240
-- g_pps_interval : NATURAL := 240
-- g_block_size : NATURAL := 32
-- g_block_size : NATURAL := 32
-- test integer case
u_20_10
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
20
,
10
);
-- 20 // 10 = 2, 20 MOD 10 = 0, 20/10 = 2 block/sync
u_22_11
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
22
,
11
);
-- 22 // 11 = 2, 22 MOD 11 = 0, 22/11 = 2 block/sync
u_39_13
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
39
,
13
);
-- 39 // 13 = 3, 39 MOD 13 = 0, 39/13 = 3 block/sync
-- test smallest nof block per sync
u_10_10
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
10
,
10
);
-- 1 block/sync
u_5_5
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
5
,
5
);
-- 1 block/sync
-- test smallest g_block_size case
u_3_3
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
3
,
3
);
-- 3 // 3 = 1, 3 MOD 3 = 0, 3/3 = 1 block/sync
u_6_3
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
6
,
3
);
-- 6 // 3 = 2, 6 MOD 3 = 0, 6/3 = 2 block/sync
u_7_3
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
7
,
3
);
-- 7 // 3 = 2, 7 MOD 3 = 1, 7/3 = 2.33 block/sync
-- test different clk_per_sync
-- test lofar case with 0.5 fraction in average nof block/sync
u_230_32_div_7_mod_6
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
230
,
32
);
-- 230 / 32 = 7, 230 MOD 32 = 6
u_20_8
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
20
,
8
);
-- 20 // 8 = 2, 20 MOD 8 = 4, 20/8 = 2.5 block/sync
u_240_32_div_7_mod_16
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
240
,
32
);
-- 240 / 32 = 7, 240 MOD 32 = 16
u_248_32_div_7_mod_24
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
248
,
32
);
-- 248 / 32 = 7, 248 MOD 32 = 24
-- test different block_size's
-- test fractional (corner) cases
u_240_27_div_8_mod_24
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
240
,
27
);
-- 240 / 27 = 8, 240 MOD 27 = 24
u_18_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
18
,
9
);
-- 18 MOD 9 = 0
u_240_30_div_8_mod_0
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
240
,
30
);
-- 240 / 30 = 8, 240 MOD 30 = 0
u_17_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
17
,
9
);
-- 17 MOD 9 = 8 = g_block_size - 1
u_19_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
19
,
9
);
-- 19 MOD 9 = 1
u_20_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
20
,
9
);
-- 20 MOD 9 = 2
u_25_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
25
,
9
);
-- 25 MOD 9 = 7
u_26_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
26
,
9
);
-- 26 MOD 9 = 8 = g_block_size - 1
u_27_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
27
,
9
);
-- 27 MOD 9 = 0
-- test some prime values
-- test some prime values
u_1
01_17_div_5_mod_16
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
101
,
17
);
-- 1
01 / 17
= 5, 1
01
MOD 17 =
16
u_1
7_3
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
17
,
3
);
-- 1
7 // 3
= 5, 1
7
MOD
3 = 2,
17
/3
=
5.66 block/sync
u_101_
23_div_4_mod_9
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
c_nof_pps
,
101
,
23
);
-- 101 /
23
=
4
, 101 MOD
23
=
9
u_101_
17
:
ENTITY
work
.
tb_dp_bsn_source_v2
GENERIC
MAP
(
101
,
17
);
-- 101 /
/ 17
=
5
, 101 MOD
17
=
16, 101/17 = 5.9411 block/sync
END
tb
;
END
tb
;
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