actual sdc rules using now when testing unb2_test_ddr*

boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc

@@ -25,18 +25,16 @@ set_time_format -unit ns -decimal_places 3
 create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK}]
 create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports {ETH_CLK}]
 
-#create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
-#create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
 
-create_clock -period 1.552 -name {SA_CLK} { SA_CLK }
-create_clock -period 1.552 -name {SB_CLK} { SB_CLK }
 create_clock -period 1.552 -name {BCK_REF_CLK} { BCK_REF_CLK }
 
 derive_pll_clocks
 derive_clock_uncertainty
 
 # Effectively set false path from this clock to all other clocks
-#set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
 #set_clock_groups -asynchronous -group [get_clocks BCK_REF_CLK]
 #set_clock_groups -asynchronous -group [get_clocks SB_CLK]
 #set_clock_groups -asynchronous -group [get_clocks SA_CLK]
@@ -44,11 +42,12 @@ derive_clock_uncertainty
 #set_clock_groups -asynchronous -group [get_clocks CLK]
 
 
+
 set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
-set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
-set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
-set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
-set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
+#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
+#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
+#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
+#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
 
 
 set_clock_groups -asynchronous -group [get_clocks pll_clk20]
@@ -60,7 +59,26 @@ set_clock_groups -asynchronous -group [get_clocks pll_clk200]
 set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
 set_clock_groups -asynchronous -group [get_clocks pll_clk400]
 
-# from Jonathan:
-#set_false_path -from [get_clocks {*cpulse_out_bus[0]}] -to [get_clocks {*wys|clk_divtx_user}]
-#set_false_path -from [get_clocks {*wys|clk_divtx_user}] -to [get_clocks {*cpulse_out_bus[0]}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_back|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_back|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
+set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
+
+set_clock_groups -asynchronous \
+-group {CLKUSR} \
+-group {SA_CLK} \
+-group {SB_CLK} \
+-group {altera_ts_clk}
+#\
+#-group [get_clocks {\Generate_XCVR_LANE_INSTANCES:?:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0|g_xcvr_native_insts[*]|tx_pma_clk }]\
+#-group [get_clocks {\Generate_XCVR_LANE_INSTANCES:?:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk }]
+
+
+
+#JTAG Signal Constraints
+#constrain the TDI TMS and TDO ports  -- (modified from timequest SDC cookbook)
+set_input_delay  -clock altera_reserved_tck 5 [get_ports altera_reserved_tdi]
+set_input_delay  -clock altera_reserved_tck 5 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck -clock_fall -fall -max 5 [get_ports altera_reserved_tdo]