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Commit 2195fb0a authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge remote-tracking branch 'origin/L2SDP-798' into DISTURB-2

parents 6da59169 c2b0cb72
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2 merge requests!277Resolve DIST2-2,!276Resolve DISTURB-2
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Stage: synthesis
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applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
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− 2
View file @ 2195fb0a
......@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /><slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /><slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /><slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /><slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
......@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10C600' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10C680' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C700' end='0x10C780' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x10C7C0' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x10C800' end='0x10C840' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10C840' end='0x10C880' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10C880' end='0x10C8C0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C8C0' end='0x10C900' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C900' end='0x10C940' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C940' end='0x10C980' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C980' end='0x10C9C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C9C0' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x10CA00' end='0x10CA20' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10CA20' end='0x10CA40' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CA40' end='0x10CA60' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10CA60' end='0x10CA80' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10CA80' end='0x10CAA0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10CAA0' end='0x10CAC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10CAC0' end='0x10CAE0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10CAE0' end='0x10CB00' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10CB00' end='0x10CB20' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10CB20' end='0x10CB40' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x10CB40' end='0x10CB50' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10CB50' end='0x10CB60' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10CB60' end='0x10CB70' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10CB70' end='0x10CB80' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10CB80' end='0x10CB90' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10CB90' end='0x10CBA0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10CBA0' end='0x10CBB0' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10CBB0' end='0x10CBB8' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10CBB8' end='0x10CBC0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10CBC0' end='0x10CBC8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10CBC8' end='0x10CBD0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10CBD0' end='0x10CBD8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10CBD8' end='0x10CBE0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10CBE0' end='0x10CBE8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10CBE8' end='0x10CBF0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10CBF0' end='0x10CBF8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10CBF8' end='0x10CC00' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10CC00' end='0x10CC08' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10CC08' end='0x10CC10' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10CC10' end='0x10CC18' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ 4
− 4
View file @ 2195fb0a
......@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
......@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>avs_common_mm</spirit:modelName>
<spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
......@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -1082,7 +1082,7 @@
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
<value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ 15
− 15
View file @ 2195fb0a
......@@ -2,7 +2,7 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:library>
<spirit:name>qsys_lofar2_unb2b_filterbank_ram_equalizer_gains</spirit:name>
<spirit:name>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
......@@ -259,7 +259,7 @@
<spirit:parameter>
<spirit:name>readLatency</spirit:name>
<spirit:displayName>Read latency</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readWaitStates</spirit:name>
......@@ -570,7 +570,7 @@
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
<spirit:modelName>avs_common_mm</spirit:modelName>
<spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
......@@ -775,7 +775,7 @@
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:name>avs_common_mm_readlatency2</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -1082,7 +1082,7 @@
</entry>
<entry>
<key>readLatency</key>
<value>1</value>
<value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
......@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
......
applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ 5
− 5
View file @ 2195fb0a
......@@ -269,7 +269,7 @@
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
<ipxact:value>1</ipxact:value>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
......@@ -626,7 +626,7 @@
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:moduleName>avs_common_mm</ipxact:moduleName>
<ipxact:moduleName>avs_common_mm_readlatency2</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
......@@ -852,7 +852,7 @@
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_bf_weights</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:name>avs_common_mm_readlatency2</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -889,7 +889,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>1</ipxact:value>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
......@@ -1169,7 +1169,7 @@
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readLatency&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;value&gt;2&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readWaitStates&lt;/key&gt;
......
applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ 17
− 17
View file @ 2195fb0a
......@@ -2,7 +2,7 @@
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:library>
<ipxact:name>qsys_lofar2_unb2c_filterbank_ram_equalizer_gains</ipxact:name>
<ipxact:name>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
......@@ -269,7 +269,7 @@
<ipxact:parameter parameterId="readLatency" type="int">
<ipxact:name>readLatency</ipxact:name>
<ipxact:displayName>Read latency</ipxact:displayName>
<ipxact:value>1</ipxact:value>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="readWaitStates" type="int">
<ipxact:name>readWaitStates</ipxact:name>
......@@ -626,7 +626,7 @@
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:moduleName>avs_common_mm</ipxact:moduleName>
<ipxact:moduleName>avs_common_mm_readlatency2</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
......@@ -852,7 +852,7 @@
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
<ipxact:library>qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:name>avs_common_mm_readlatency2</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
......@@ -889,7 +889,7 @@
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>1</ipxact:value>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
......@@ -909,7 +909,7 @@
type = "String";
}
}
element qsys_lofar2_unb2c_filterbank_ram_equalizer_gains
element qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains
{
}
}
......@@ -1169,7 +1169,7 @@
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readLatency&lt;/key&gt;
&lt;value&gt;1&lt;/value&gt;
&lt;value&gt;2&lt;/value&gt;
&lt;/entry&gt;
&lt;entry&gt;
&lt;key&gt;readWaitStates&lt;/key&gt;
......@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+ 27
− 11
View file @ 2195fb0a
......@@ -92,6 +92,8 @@ ARCHITECTURE str OF sdp_beamformer_output IS
SIGNAL dp_offload_tx_src_in : t_dp_siso;
SIGNAL ip_checksum_src_out : t_dp_sosi;
SIGNAL ip_checksum_src_in : t_dp_siso;
SIGNAL dp_pipeline_ready_src_out : t_dp_sosi;
SIGNAL dp_pipeline_ready_src_in : t_dp_siso;
SIGNAL common_fifo_rd_req : STD_LOGIC;
SIGNAL payload_err : STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -269,6 +271,20 @@ BEGIN
src_in => ip_checksum_src_in
);
-------------------------------------------------------------------------------
-- dp_pipeline_ready to ease timing closure
-------------------------------------------------------------------------------
u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
PORT MAP(
rst => dp_rst,
clk => dp_clk,
snk_out => ip_checksum_src_in,
snk_in => ip_checksum_src_out,
src_in => dp_pipeline_ready_src_in,
src_out => dp_pipeline_ready_src_out
);
-------------------------------------------------------------------------------
-- mms_dp_xonoff
-------------------------------------------------------------------------------
......@@ -289,8 +305,8 @@ BEGIN
dp_clk => dp_clk,
-- ST sinks
snk_out_arr(0) => ip_checksum_src_in,
snk_in_arr(0) => ip_checksum_src_out,
snk_out_arr(0) => dp_pipeline_ready_src_in,
snk_in_arr(0) => dp_pipeline_ready_src_out,
-- ST source
src_in_arr(0) => src_in,
src_out_arr(0) => out_sosi
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+ 1
− 4
View file @ 2195fb0a
......@@ -120,10 +120,7 @@ BEGIN
g_gain_w => c_sdp_W_bf_weight,
g_in_dat_w => c_sdp_W_subband,
g_out_dat_w => c_gain_out_dat_w,
g_gains_file_name => g_gains_file_name,
-- extra input latency to ease timing.
g_pipeline_real_mult_input => 2,
g_pipeline_complex_mult_input => 2
g_gains_file_name => g_gains_file_name
)
PORT MAP (
-- System
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+ 1
− 4
View file @ 2195fb0a
......@@ -120,10 +120,7 @@ BEGIN
g_gain_w => c_sdp_W_sub_weight,
g_in_dat_w => c_sdp_W_subband,
g_out_dat_w => c_gain_out_dat_w,
g_gains_file_name => g_gains_file_name,
-- extra input latency to ease timing.
g_pipeline_real_mult_input => 2,
g_pipeline_complex_mult_input => 2
g_gains_file_name => g_gains_file_name
)
PORT MAP (
-- System
......
libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+ 2
− 6
View file @ 2195fb0a
......@@ -165,13 +165,9 @@ BEGIN
IF dp_on_pps = '1' THEN
nxt_sync <= '1'; -- ensure issue sync at first sync interval for start at PPS.
IF pps = '1' THEN
IF UNSIGNED(bsn_time_offset) = 0 THEN
nxt_state <= s_dp_on_sop;
ELSE
nxt_bsn_time_offset_cnt <= (OTHERS=>'0');
nxt_state <= s_bsn_time_offset;
END IF;
END IF;
ELSE
nxt_state <= s_dp_on_sop;
END IF;
......
libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+ 3
− 1
View file @ 2195fb0a
......@@ -36,6 +36,8 @@
-- RAM init files (.hex files) only work when g_gains_write_only is set to
-- FALSE.
-- . The gains memories are single page.
-- . The MM interface (ram_gains_mosi/miso) has a read latency of 2. Therefore,
-- choose the correct avs_common_mm_readlatency2 when creating the qsys system.
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
......@@ -100,7 +102,7 @@ ARCHITECTURE str OF mms_dp_gain_serial_arr IS
-- dat_w : NATURAL;
-- nof_dat : NATURAL; -- optional, nof dat words <= 2**adr_w
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
CONSTANT c_mm_ram : t_c_mem := (latency => 1,
CONSTANT c_mm_ram : t_c_mem := (latency => 2, -- set latency to 2 to ease timing
adr_w => ceil_log2(g_nof_gains),
dat_w => sel_a_b(g_complex_gain, c_nof_complex, 1) * g_gain_w,
nof_dat => g_nof_gains,
......
libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+ 1
− 1
View file @ 2195fb0a
......@@ -57,7 +57,7 @@ ARCHITECTURE tb OF tb_mms_dp_gain_serial_arr IS
CONSTANT c_mm_clk_period : TIME := 20 ns;
CONSTANT c_dp_clk_period : TIME := 10 ns;
CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
CONSTANT c_dut_latency : NATURAL := 4; -- = 3 for the real or complex multiplier + 1 for the RAM read latency
CONSTANT c_dut_latency : NATURAL := 5; -- = 3 for the real or complex multiplier + 2 for the RAM read latency
CONSTANT c_real_multiply : BOOLEAN := g_complex_data=FALSE AND g_complex_gain=FALSE;
CONSTANT c_nof_gains_w : NATURAL := ceil_log2(g_nof_gains);
......
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